Patents Examined by Derrie Holt Banks
  • Patent number: 6024634
    Abstract: A grinding product and a method of making same. The grinding product comprises a woven or knitted cloth of multifilament threads (1) whose fibers (2) form projecting loops (3), and separate agglomerates (4) of grinding material applied to the loops. During the grinding, different sides of the agglomerates (4) come into contact with the surface to be ground, which prolongs the service life of the grinding product. The agglomerates also form a gap between the cloth and the surface to be ground, through which gap the grinding dust can be removed.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: February 15, 2000
    Assignee: OY KWH Mirka AB
    Inventors: Goran Hoglund, Hans Hede
  • Patent number: 5947807
    Abstract: A cleaning and polishing assembly having a compressible main body with a releasable attachment material on one face and a fibrous working surface on its other face. The fibrous working surface is composed of fibers having a trilobal cross-section. The cleaning and polishing pad can be mounted on a power drive tool, or in a hand-actuated embodiment, can be mounted to a gripping pad specially adapted for hand use.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: September 7, 1999
    Inventor: Elmo R. Overseth
  • Patent number: 5934973
    Abstract: A semiconductor wafer dicing saw is controlled by monitoring blade exposure from a flange holding the blade during the wafer dicing process. As the wafer is cut and separated into discrete electronic chips, the dicing blade wears. As the blade is brought closer and closer toward the wafer during cutting, the blade exposure is continuously being reduced. The small dimensions, coolant flow, and close tolerances typical in the wafer dicing process, do not permit visual inspection. Excess blade wear and thus reduced exposure or flange clearance between the blade cutting edge and flange edge will cause damage to the wafer and blade by restricting coolant flow or by contact of the flange with the wafer.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: August 10, 1999
    Inventors: John N. Boucher, David E. Bajune
  • Patent number: 5913715
    Abstract: A process of conditioning a polishing pad used in chemical mechanical polishing of an integrated circuit and having a glazed layer is described. The process includes introducing a conditioning reagent including at least one of hydrofluoric acid, buffered oxide etch composition and potassium hydroxide on the polishing pad to dissolve at least a portion of the glazed layer; and abrading the glazed layer and disloding at least some particles from the glazed layer.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: June 22, 1999
    Assignee: LSI Logic Corporation
    Inventors: Eric J. Kirchner, Jayashree Kalpathy-Cramer