Abstract: A central processing unit includes a programmable logic array, a timing control unit, a predecoder, a data input/output part, and a processing part. The processing part carries out a predetermined operation on m-bit low-order data from among data which is composed of n bits and which is read out from a memory and m-bit high-order data from among the data composed of n bits, and outputs a carry signal when the predetermined operation on the m-bit low-order data results in a carry. When the operation code is a read modify write instruction and when the processing part outputs the carry signal, the programmable logic array controls the input/output part so that only the result of the predetermined operation on the m-bit low-order data is written into the memory.