Patents Examined by Deven Couzos
  • Patent number: 5897327
    Abstract: A MOS capacitor in which an insulating layer of thermal oxide film is disposed between the electrode 2 and the silicon wafer 1 is formed. While a light beam of an energy larger than 1.1 eV is irradiated on the electrode 2 and its periphery, electrons inject from the electrode 2 side (voltage is applied from the silicon wafer 1 side). The injected electrons are activated by the light irradiation. For both p-type or n-type semiconductor, the dielectric breakdown electric field strength can be precisely measured according to the degree of processing defects. The evaluation method is particularly effective for the n-type semiconductor wafer, which was difficult to evaluate by the prior art.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: April 27, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Eiichi Asano, Hisami Motoura, Yasuhiro Shimada