Patents Examined by Deven M. Collins
  • Patent number: 6297077
    Abstract: The invention comprises a chip card, a process for making the chip card, and an injection molding device for the implementation of the process, wherein a mold in the injection molding device includes a minimum of one mold space and mold parts which are movable in relation to each other, whereby: a first injection nozzle is provided for injecting a first plastic material into a first mold compartment in the mold space; a second injection nozzle is provided for injecting a second plastic material into a second mold compartment in the mold space, and; in a preferred embodiment, the first injection nozzle is positioned vertically to the second injection nozzle.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: October 2, 2001
    Assignee: Orga Kartensysteme GmbH
    Inventor: Dirk Fischer
  • Patent number: 6238952
    Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip wherein the die pad and the connection pads have a concave profile. A package body is formed over the semiconductor chip, the die pad and the connection pads in a manner that a potion of the die pad and a portion of each connection pad extend outward from the bottom of the package body. The present invention further provides a novel method of producing the low-pin-count chip package described above.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: May 29, 2001
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chun Hung Lin
  • Patent number: 6140701
    Abstract: A multilayer structure is provided which suppresses hillock formation due to post-heat treatment steps in thin aluminum films deposited on other substrates by sandwiching the aluminum film between thin layers of aluminum titanium nitride. The first aluminum titanium nitride layer acts as a compatibilizing layer to provide a better match between the coefficients of thermal expansion of the substrate and aluminum metal layer. The second aluminum titanium nitride layer acts as a cap layer to suppress hillock formation.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: October 31, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Kanwal K. Raina, Tianhong Zhang, Allen McTeer
  • Patent number: 6071755
    Abstract: A semiconductor device includes an encapsulating resin encapsulating a semiconductor substrate, a lead pattern or a laminated wiring layers transferred or secured on the lower surface of the encapsulating resin and a plurality of external electrode disposed on the lower surface of the lead pattern. The device may be manufactured by bonding a semiconductor substrate to a transferring substrate on which a lead pattern is formed, resin encapsulating an upper portion of the transferring substrate to cover the semiconductor substrate, and removing only the transferring substrate with the lead pattern left bonded to the encapsulating resin and the semiconductor substrate.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: June 6, 2000
    Assignee: Mitsubushi Denki Kabushiki Kaisha
    Inventors: Shinji Baba, Jun Shibata, Tetsuya Ueda
  • Patent number: 6069072
    Abstract: A structure and method incorporating a CVD TiN barrier layer 230 over the aluminum plug 220 in order to prevent the high plug resistance caused by the blanket metal film stack 240, 250, and 260 deposition process. Unlike physical vapor deposited (PVD) TiN, CVD TiN 230 does not react with the aluminum 220 during annealing. CVD TiN has also been shown to be a better diffusion barrier for aluminum than PVD TiN. In addition, CVD TiN will disrupt any unfavorable grain boundary propagation through the aluminum plug which may act as a source of electromigration failure. Therefore, the CVD TiN 230 can increase the electromigration resistance, without increasing the contact/via resistance.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: May 30, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Anthony J. Konecni, Girish Anant Dixit
  • Patent number: 6066542
    Abstract: Component structures of, for example, IGBTs are manufactured on the respective top sides of two substrates, the substrates are thinned proceeding from their respective back sides, and, after polishing, the back sides of the thinned substrates are durably electrically conductively connected to one another by wafer bonding.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: May 23, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Daniel Reznik, Hans-Joachim Schulze, Wolfgang Eckhard