Patents Examined by Devin Collins
  • Patent number: 5960258
    Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: September 28, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Walter L. Moden
  • Patent number: 5937276
    Abstract: A connection component for a semiconductor chip includes a support structure having a top surface including a dielectric material and a bottom surface. The support structure includes a central portion, a peripheral portion and one or more gaps extending substantially between the central portion and the peripheral portion. A bus overlies the top surface of the support structure. The each bus has an outer edge which overlies the peripheral portion of the support structure and an inner edge which overlies the one or more gaps. The support structure also includes one or more electrically conductive leads having first ends secured to the central portion and second ends overlying the gaps and being secured to the inner edge of the bus. The second ends of the leads are displaceable relative to the bus in response to bonding forces being applied to the leads for engaging contacts on a semiconductor chip.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: August 10, 1999
    Assignee: Tessera, Inc.
    Inventor: Thomas H. Distefano
  • Patent number: 5918144
    Abstract: When BLM films as a barrier metal under solder balls are deposited to Al pad electrodes by a lift-off method utilizing a deformed resist pattern, a wafer is heated before sputter-forming of the BLM film, thereby eliminating a water content contained in a first layer polyimide film. In an rearrangement process, a wiring connecting the electrode pad and the solder ball is formed with the BLM film. Since degassing upon sputter forming of the BLM film is suppressed by the elimination of the water content, peeling of the BLM film on the first layer polyimide film is prevented. The wafer may also be heated simultaneously with the formation of the deformed resist pattern by Ar.sup.+ reverse sputtering (into overhang shape). Adhesion between the surface protection film and the BLM film upon rearrangement of the solder balls is thus improved in the flip chip bonding method.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: June 29, 1999
    Assignee: Sony Corporation
    Inventor: Toshiharu Yanagida
  • Patent number: 5904488
    Abstract: A semiconductor integrated circuit device includes: a base film made of insulating material; a wiring pattern of a predetermined shape formed on the base film; a semiconductor chip provided on the base film, wherein an electrode terminal of the semiconductor chip comes into contact with one end of the wiring pattern; and a flexible protective film having an insulating property, the flexible protective film being adhered onto the base film while it covers the semiconductor chip and one end of the wiring pattern.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: May 18, 1999
    Assignee: Shinko Electric Industries Co. Ltd.
    Inventor: Shigetsugu Muramatsu