Abstract: A method of packaging a semiconductor device (10) partitions a distribution substrate (20, 40) into regions (31-34) such that attachment points (22) for electrically coupling to the semiconductor device lie in a first region (31). A first set of conductors are routed from a portion of the attachment points to terminals in a second region (32). Another portion of the attachment points are assigned to available routing channels of the second region for disposing a second set of conductors across the second region to a third region (33). Partitioning improves routing efficiency without requiring objects to be located on grid points or restricting the angles of the routing channels.

Abstract: A method of embedding a magnetically attractable member (25) in a ceramic material (1) and a system therefor wherein there are provided a magnetically attractable member and a ceramic member capable of being placed in a molten state. The magnetically attractable member is disposed over the ceramic member and the ceramic member is placed in a molten state. The magnetically attractable member is then disposed in the molten ceramic member by magnetic attraction and the molten ceramic member is then hardened around the magnetically attractable member. The magnetically attractable member is taken from the class consisting of Alloy 42 and Kovar. The ceramic member is preferably a glass. The ceramic member is preferably disposed on a semiconductor package and the magnetically attractable member is preferably at least a portion of a semiconductor lead frame.

Abstract: A semiconductor device comprises a square-shaped first semiconductor chip having a first LSI, a square-shaped second semiconductor chip having a second LSI, which is smaller in size than the first semiconductor chip and connected to the first semiconductor chip by face down bonding, and a square-shaped package made of a molding resin for packaging the first and second semiconductor chips. The respective centers of the first and second semiconductor chips are offset from each other, while the center of the second semiconductor chip is substantially coincident with the center of the molding resin.

Abstract: A method for semiconductor chip packaging comprises the following processes: preparing an array-typed base plane by pressing a plane-shaped material, wherein said array-typed base plane comprises a plurality of single-united base surrounded and defined by latticed dams; mounting a already-cut die to each said base unit on said array-typed base plane, and adhering said die to said base unit; wire-bonding said mounted die; applying adhesive paste to top surface of each said dam, and covering the resultant structure with a transparent lid to ensure the hermeticity of the package; cutting said array-typed base plane to a plurality of single-united base. By above-mentioned process, the manufacturing cost can be reduced and the yield can also be enhanced.

Abstract: A semiconductor chip such as a cold cathode is mounted on a base plate using a conventional solder or like metallic eutectic material or conductive paste, and then secured to the base plate using an inorganic adhesive or like material, which is capable of being hardened at a temperature lower than the mounting temperature, and the bonding strength of which is not deteriorated even at higher temperatures.

Abstract: A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

Abstract: Disclosed is a method of fabricating a programmable antifuse structure wherein programming of the antifuse structure results in conducting paths which are confined within a finite predictable area. The method includes depositing an insulating layer over a field. Additionally, the method includes creating a via through a via area of the insulating layer to expose a programmable surface area of the field. The method also includes depositing an interlayer over the exposed programmable surface of the field, over sidewalls of the via, and over an extended surface region of the insulating layer, the extended surface region including the via area. The method includes depositing a first conducting layer over the interlayer. The method also includes etching in the extended surface region to the insulating layer; the etching is for confining formation of conductive paths to within the via area upon programming of the programmable antifuse structure.

Abstract: Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.