Abstract: A disk drive controller integrated circuit includes a programmable servo burst decoder that can process any one of a plurality of servo sectors. A disk drive head reads each embedded servo sector on the disk and provides an analog signal, a servo burst, representing the servo sector to a preamp. The preamp provides an amplified analog signal to a read channel integrated circuit. The read channel integrated circuit provides input signals that are processed by the programmable servo burst decoder. The programmable servo burst decoder includes a programmable timing mark sequencer having an instruction register of a first size and a servo timing mark output line, and a programmable burst sequencer connected to the servo timing mark output line and having an instruction register of a second size. In this embodiment, the first size is different from the second size. Specifically, the first size is 20 bits, and the second size is 38 bits.

Abstract: A Harvard architecture data processing system includes a processor, main memory, an instruction cache, and a data cache. As is generally known with the Harvard architecture, these components are interconnected by an instruction bus, an instruction address bus, a data bus, and a data address bus. The instruction cache includes a branch target section and a general instruction section. For each instruction request by the processor, both sections are examined to determine if the requested instruction is in the cache. If it is, it is transmitted from the cache to the processor. If it is not, an instruction line including the requested instruction is fetched from main memory. If the requested instruction represents a jump (the result of an unconditional branch or a conditional branch the condition of which is met) the fetched instruction line can be stored only in the branch target section.

Abstract: A method and apparatus for generating an interactive component data stream, representing an application program, for an audio video interactive (AVI) composite signal, is disclosed. The method comprises the following steps. First, program files representing the application program are generated. Then, flow data defining the data structure of the interactive component is generated. Finally the data stream is generated by selectively inserting program files into the data stream in response to the flow data. Apparatus for generating such an interactive component data stream comprises a source of program files representing the application program and a source of flow data defining the data structure of the interactive component. A flow builder selectively inserts files from the source of files into the interactive component in response to data from the flow data source.

Abstract: A plurality of digital modules on a Futurebus Plus common system bus means in a network are connected by the Futurebus Plus system bus for transfer of data between modules. A sending module (master) transmits address and message data on the bus to a receiving module (slave). Each module provides an interface having a Longitudinal Redundancy Checker such that the sending module transmits a first check word to the receiving module which generates a second check-word. If these check words match, then the data is accepted as good. Thus, the network can work continuously using the system bus even while new digital modules are inserted onto the system bus or detached from the system bus.

Abstract: Two units are disclosed, one of which is installed in the computer and one of which is located remotely and includes the antenna and radio frequency transmitter and receiver elements. The two units communicate over an infrared (IR) link. The data is transmitted between the two units as real and imaginary components using separate IR signals. By using real and imaginary digitized signals, great flexibility is provided as to the actual contents and protocols capable of being utilized and serial digital data can be provided from the computer and received in the computer using only simple table look-ups. The antenna unit includes personalization by way of differing filters and software to allow it to operate with a plurality of radio channels and protocols. Each unit has a serial number to identify itself and to keep a communication link secure once established.

Abstract: An external memory unit for a data processing system has a plurality of detachable memory media. Data is written in parallel to the memory media. Since the positions of the memory media can be switched, reference information is written in each of the media during an initialization process. Once initialized, the data can be read from and written to the memory media regardless of their current and former positions in the external memory unit. The reference information has sequence information indicating the position of a memory medium in a sequence when data is first written to a group of media as part of an operation that subdivides data and writes the subunits to the group. The name of the group is also included in the reference information. When a subsequent read or write operation is requested, the group information is used to determine if all of the media required for executing the request are present in the external memory unit, and if so, the operation is executed.

Abstract: A real-time data processing system employs a control computer which defines a pre-processing arrangement of data channels to speed processing, and an arrangement of output data channels to provide a desired output format. The data channels are samples and arranged into a data packet which is passed to an array of digital signal processors (DSPs) arranged in a series of stages, with at least one DSP per stage. A front-end DSP receives the data packet and appends a control field having commands addressed to specific DSPs to the data packet along with adding a monitor field. The DSPs monitor the control field for commands addressed to it and then executes those. The status of the operation is written in the monitor field and the data packet is passed to DSPs of the next stage for `pipelined` processing. DSPs of the last stage collect the process portions of the data packet, assemble them according to the desired output format and pass on the completed data packet.

Abstract: In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the contents of the accumulator and supplementary accumulator registers without the burden of speed penalties is addressed and solved. This is achieved by providing input/output access to a common register file and by switching control of the register file to the proper processing unit appropriately. A single, shared accumulator register and a single, shared supplementary accumulator register are included in the stack along with other sharable registers such as address modification registers. Thus, the contents of the accumulator register and the supplementary accumulator register are always up-to-date and available to all processing units in the central processor without the need for first carrying out rationalization steps.