Abstract: A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adder 1604 selectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier array 1603 and data output from adder 1604.

Abstract: The present invention is a method and apparatus for testing random numbers generated by a random number generator in real time. A stream of random bits is generated using said random number generator, then the generated random bits undergo a gap length calculation operation in which all sub-sequences having identical bit patterns are identified and the resulting gap lengths are applied to exponential averaging to obtain average gap lengths between identical bit patterns. The average gap lengths are compared to at least one predetermined acceptance range, so that if at least one of the average gap lengths falls repeatedly outside the predetermined acceptance range more than a predetermined number of times, it is determined that the generated random bits are insufficiently random.

Abstract: A system and method for parallel computation of Discrete Sine and Cosine Transforms. The computing system includes a plurality of interconnected processors and corresponding local memories. An input signal x is received, partitioned into P local vectors xi, and distributed to the local memories. The preprocessors may calculate a set of coefficients for use in computing the transform. The processors perform a preprocess in parallel on the input signal x to generate an intermediate vector y. The processors then perform a Fast Fourier Transform in parallel on the intermediate vector y, generating a second intermediate vector a. Finally, the processors perform a post-process on the second intermediate vector a, generating a result vector v, the Discrete Transform of signal x. In one embodiment, the method generates the Discrete Sine Transform of the input signal x. In another embodiment, the method generates the Discrete Cosine Transform of the input signal x.

Abstract: A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a “critical” stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. In a preferred configuration having P RAM partitions and P RADIX stages, the critical stage is stage number log2 P, and until the critical stage, only P/2 RADIX elements can simultaneously operate within each stage. After the critical stage, all RADIXes within each stage can simultaneously operate.