Abstract: According to an embodiment, there is provided a fabricating method for a thin film transistor substrate divided into a display area displaying images and a non-display area beside the display area, the fabricating method comprising: forming a gate wire in the display area, a common voltage line for a MPS (mass production system) test in the non-display area, and a grounding line for the MPS test in the non-display area with same material at the same time; forming a gate insulating layer covering the gate wire and a first insulating layer covering the common voltage line for the MPS test and the grounding line for the MPS test with same material at the same time; forming a data wire crossing the gate wire and defining a pixel area in the display area; and forming a pixel electrode in the pixel area and an electrode layer on the first insulating layer corresponding to the common voltage line for the MPS test and the grounding line for the MPS test with same material at the same time.

Abstract: A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions.

Abstract: The invention provides an integrated framework for detecting peripheral sympathetic responses through imaging. The measurements may be performed on three facial areas of sympathetic importance, that is, periorbital, supraorbital, and maxillary. Because the imaging measurements are thermal in nature and comprise multiple components of variable frequency (i.e., blood flow, sweat gland activation, and breathing), wavelets are used as the image analysis framework. The image analysis may be grounded on GSR signals.

Abstract: Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line.

Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: Disclosed herein is a noise canceling apparatus including: a microphone configured to pick up ambient sound as noise; a first signal generator configured to receive a signal from the microphone to generate a noise cancel signal that is inverted in phase to the signal received from the microphone and has an amplitude level considered with an attenuation in accordance with a distance from the microphone to an observation point separated away from the microphone; a first loudspeaker configured to be arranged in the proximity of the microphone and output the noise cancel signal; a second signal generator configured to receive the signal from the microphone to generate a positive-phase signal that has the same phase as that of the signal from the microphone; and a second loudspeaker configured to be arranged in the proximity of the microphone and output the positive-phase signal.

Abstract: An active noise reduction system that reduces the incidence of divergence in the presence of high amplitude interfering noise. A limited frequency range threshold is established.

Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.

Abstract: An integrated circuit having memory disposed thereon and method of making thereof includes a standard dimension carrier substrate and an information router integrated on the carrier substrate. Further included therein is at least one system memory integrated on the carrier substrate and in electrical communication with the information router across at least one of the electrical leads associated with the carrier substrate. Thereupon, system instructions may be stored and retrieved from the system memory through the information router within the integrated circuit on the standard dimension carrier substrate.

Abstract: A bipolar transistor for semiconductor device has a collector region having a first conductivity type disposed on a surface of a semiconductor substrate having the first conductivity type. A base region having a second conductivity type is disposed in the collector region. An emitter region having the first conductivity type is disposed in the base region. A high concentration first conductivity type region for a collector electrode is disposed in the collector region. A high concentration second conductivity type region for a base electrode is disposed in the base region. The high concentration first conductivity type region for a collector electrode and the high concentration second conductivity type region for a base electrode contact directly with each other so that the collector region and the base region have a same potential.

Abstract: A semiconductor photo detecting element includes a PIN-type photo detecting element and window semiconductor layer. The PIN-type photo detecting element has a semiconductor substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer is provided on the semiconductor substrate, is lattice-matched to the semiconductor substrate, includes a first conductivity type dopant, and has first band gap energy. The second semiconductor layer is provided on the first semiconductor layer, has the first band gap energy, and has a concentration of the first conductivity type dopant lower than that of the first semiconductor layer or is substantially undoped. The third semiconductor layer is provided on the second semiconductor layer. The window semiconductor layer has second band gap energy larger than the first band gap energy at a light-incoming side with respect to the second semiconductor layer and has a thickness of 5 nm to 50 nm.

Abstract: An audio reproducing apparatus includes a power supply, an amplifier, a speaker, and a controller. The power supply is for supplying a voltage. The amplifier is for receiving the voltage and audio signals, amplifying the audio signals, and outputting amplified audio signals. The speaker is for reproducing sound after receiving the amplified audio signals. The controller is for receiving the voltage and generating a control signal to enable the amplifier. The controller includes a generator and a delay unit. The generator is for receiving the voltage and generating the control signal. The delay unit is for delaying the time of transferring the voltage from the power supply to the generator.

Abstract: A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive through hole vias (THV) are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.

Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.

Abstract: A memory cell has a floating gate electrode, a first inter-gate insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the first inter-gate insulating film. An FET has a lower gate electrode, a second inter-gate insulating film having an opening and arranged on the lower gate electrode, a block film having a function to block diffusion of metal atoms and formed on at least the opening, and an upper gate electrode connected electrically to the lower gate electrode via the block film and arranged on the second inter-gate insulating film. The control gate electrode and the upper gate electrode have a Full-silicide structure.

Abstract: A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation plate at the same time.

Abstract: A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is formed through the insulating layer. A plurality of conductive traces is formed over the surface of the semiconductor die electrically connected between the bond pads and conductive THVs. The semiconductor die are stacked to electrically connect the conductive THVs between adjacent semiconductor die. The stacked semiconductor die are mounted within an integrated cavity of a substrate or leadframe structure. An encapsulant is deposited over the substrate or leadframe structure and the semiconductor die. A thermally conductive lid is formed over a surface of the substrate or leadframe structure. The stacked semiconductor die are attached to the thermally conductive lid.

Abstract: A display apparatus including a TFT array substrate on which TFTs are formed in an array, a counter substrate disposed so as to face the TFT array substrate, and a sealing pattern for adhering the TFT array substrate and the counter substrate to each other, wherein the counter substrate has a counter electrode, and the TFT array substrate has a first conductive layer, a first insulating film formed on the first conductive layer, a second conductive layer disposed so as to intersect the first conductive layer via the first insulating film, a second insulating film formed on the second conductive layer and having at least two layers, and common electrode wiring provided below the sealing pattern and electrically connected to the counter electrode by the sealing pattern, and the sealing pattern overlaps the second conductive layer via the second insulating film.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.