Abstract: A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.
Type:
Grant
Filed:
October 28, 2005
Date of Patent:
July 3, 2007
Assignee:
Semiconductor Manufacturing International (Shanghai) Corporation
Abstract: A clock frequency divider circuit including: a storing section for storing an input signal in synchronism with an input clock signal; a supplying section for supplying, as the input signal, one of a first value obtained by adding a value stored by the storing section to a numerator setting value and a second value obtained by subtracting a denominator setting value from the first value; a retaining section for retaining a most significant bit of the value stored by the storing section in synchronism with the input clock signal; and a logical product generating section for generating a logical product of a value retained by the retaining section and the input clock signal, and outputting the logical product as an output clock signal; wherein the supplying section supplies one of the first value and the second value as the input signal on a basis of the most significant bit of the value stored by the storing section.
Abstract: Various devices, circuits and systems including filter sections for creating complex poles are described herein. For example, various circuits including transistors, tuning capacitors and resistors are described. In the circuits, the tuning capacitor is electrically coupled between the gate and source of the transistor, and the resistor is electrically coupled to the gate of the transistor. In one configuration, the circuit input is applied to the gate of the transistor via the resistor, and the output is taken from the source of the transistor. In another configuration, the input is applied to the source of the transistor, and the output is taken from the same source. In yet another configuration, the input is applied at the source of the transistor and the output is taken from the drain of the transistor.
Type:
Grant
Filed:
February 2, 2006
Date of Patent:
March 27, 2007
Assignee:
Agere Systems Inc.
Inventors:
James A. Bailey, Michael E. Butenhoff, Raymond Chik, Angus McLaren, William Martin Snelgrove