Abstract: When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.

Abstract: A multimedia collaboration system that integrates separate real-time and asynchronous networks--the former for real-time audio and video, and the latter for control signals and textual, graphical and other data--in a manner that is interoperable across different computer and network operating system platforms and which closely approximates the experience of face-to-face collaboration, while liberating the participants from the limitations of time and distance. These capabilities are achieved by exploiting a variety of hardware, software and networking technologies in a manner that preserves the quality and integrity of audio/video/data and other multimedia information, even after wide area transmission, and at a significantly reduced networking cost as compared to what would be required by presently known approaches. The system architecture is readily scalable to the largest enterprise network environments.

Abstract: First and second parallel processors operate in one of plural modes including synchronous and stand-alone modes. Each processor includes a clock for selectively providing a first high frequency clock signal to both processors. Each processor also includes electronic circuitry operating at a second frequency lower than the first frequency which generates a clock selection signal that selects one of the clocks from the first and second processors to clock both processors. The electronic circuitry, in response to mode change signals, generates clock switching control signals at the lower frequency. The lower frequency clock control signals are reclocked so that they are synchronous with the first frequency clock signals before being used to select one of the clocks.

Abstract: A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.

Abstract: An embedded computer, CaTbox, is connected to a PC via SCSI cable, and to a telecommunications switch. CaTbox runs an operating system, CaTOS, and contains a hard disk accessible to PC as a SCSI disk called CaTdisc. Print jobs issued from PC are transferred as files to CaTdisc, queued by CaTOS and driven in the foreground to a printer attached to CaTbox. CaTbox has an LCD screen, keypad, and is connected to telephone handsets. While PC and printer are off, CaTbox receives faxes, voicemail, email and stores them on CaTdisc. It delivers HTML pages stored on CaTdisc. Keypad directed, CaTbox plays voicemail and prints faxes or email. Modems on CaTbox, CaTmodems, are available for data, voice, fax communications from PC. A scanner on SCSI bus may be driven by CaTbox via keypad to scan documents to store on CaTdisc, print or send as faxes. CaTOS has step tables for each modem, actions, foreground programs, configuration files, and queues.

Abstract: A method for performing data transfers in a computer system comprising an improved DMA controller (DMAC) for performing DMA transfers between a peripheral device and system memory and receiving and servicing interrupts generated by the peripheral device. The system comprises a CPU, system memory, the DMA controller and a plurality of peripheral devices interconnected by buses. The CPU programs the peripheral, such as a disk drive, to retrieve or store data. When the peripheral has retrieved the data or is ready to receive the data the peripheral generates an interrupt. The CPU programs the DMAC to perform DMA transfers between the peripheral and the system memory and to selectively decouple the interrupt request from the peripheral to the CPU so that the DMAC can service the interrupt from the peripheral rather than the CPU. The decoupling is selectively performed so that, in the case of a write to the peripheral, the DMAC can receive the interrupt from the peripheral and perform the data transfer.

Abstract: The present invention pertains integrated circuit method and apparatus for achieving the optimum computation performance of document data types. The integrated circuit maintain a digital dictionary for editing, storage, updating, referencing, and retrieval of vocabulary data structure corresponding to selective subject of interest as defined by each user or application. The integrated circuit further directly retrieve, execute, and evaluate the external incoming document according to said selective subject of interest in order to confirm whether the selective user or application have interest in this document. The integrated circuit further directly interpret, and execute the incoming document and the corresponding procedural calls provided particular subject of interest can be confirmed. The present invention produce, maintain, and retrieve user or application specific multimedia reference material for each generic text based document.

Abstract: A computer system comprising a multiprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network and interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address.

Abstract: The transports available in a local computer system for communicating with a remote computer system are automatically determined at either install time or run time. At install time, a list of transports supported by the local computer system is used to determine which supported transports are actually installed in the local computer system and the media dependent modules (MDMs) that correspond to those installed transports. At run time, a list of the installed transports and corresponding MDMs is used to determine which installed transports (and corresponding MDMs) can actually be used for an impending communications session with the remote computer system.

Abstract: An integrated circuit of this invention includes a processor, a first circuit for generating a clock signal, and a second circuit for selecting a suitable line voltage. The first circuit generates at least two kinds of clock signals. When one kind of clock signal having a high frequency is selected for use, the processor gives an instruction to the second circuit so as to change the connection between external batteries, and so, to obtain a high line voltage. On the contrary, when the other kind of clock signal having a low frequency is selected for use, said processor gives an instruction to the second circuit so as to change the connection between the batteries, and so, to obtain a low line voltage.

Abstract: An open network system for supporting input/output (I/O) operations for non-standard I/O devices are disclosed. The system includes a server coupled to a plurality of I/O devices through an open network and an extended open system protocol that supports communication with devices that are not personal computers (PCs). These devices include magnetic stripe readers, check readers, smart card readers, credit card terminals, screen phone terminals, PIN pads, printers, and the like. The extended open network protocol includes tags which identify device and input operations and attributes which identify the location, data exchange method, and data variable names for the retrieval, acquisition, and submission of data between the server and I/O devices. Preferably, the open network protocol is implemented in a Hyper Text Transport Protocol (HTTP).

Abstract: A pair of SONET rings (12' and 14') can be interworked by providing at least two gateways (16.sub.m-1 and 16.sub.m) that are shared by each of the rings. Each shared gateway has the capability of transferring a block of optical information resident in a prescribed time slot in an interchange frame associated with one ring to a time slot in an interchange frame associated with the other ring so the block reaches its intended destination in that ring.

Abstract: A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it.

Abstract: The invented controller is the combination of: an intelligent interface to a SCSI bus, a multi-port buffer memory manager, a formatter, and a local processor port. With the addition of a few components for the device-level interface, the invented controller along with a buffer RAM, a local processor system, and an optional data separator completes a high performance disk, or other mass storage, controller subsystem. The invention is particularly directed to (1) the dual use of a buffer memory as data buffer storage and for storage of instructions to be executed by a SCSI-protocol processor, (2) the architecture of the interface to the SCSI bus, and (3) the instruction set of the SCSI-protocol processor.

Abstract: A shared object is created which is copied to all system nodes requiring access to the object and a used-by table is created identifying the nodes holding a copy of the object. When the object is updated by operations at one of the nodes then the copies identified by the used-by table are also updated.

Abstract: A wireless network is initialized by communications between mobile units forming an ad hoc network or by communications between a mobile unit and an access point unit. Mobile units transmit announcements in order to establish a communication link. To ensure the announcements are received, the mobile units scan different frequencies at various times using various hop sequences. Once communication is established, one mobile unit adopts the hop frequency of the other mobile unit according to a comparison between the hop frequencies of the two units. Multiple mobile units initialize to form ad hoc networks in similar manner.

Abstract: A simple method and apparatus for posting hypertext documents to a hypertext server so as to make the hypertext documents accessible to users of the hypertext document system while securing against unauthorized modification of the posted hypertext documents. The hypertext documents form a portion of the World Wide Web and a process for posting hypertext documents begins with an author authoring the hypertext pages on a client computer, sending an add request to a server computer, causing the generation of a unique identifier for the author of the hypertext document, obtaining a charge authorization from the author, and sending a database entry request from the client to the server comprising the unique identifier, the charge authorization and the hypertext files comprising the document.

Abstract: A preferred embodiment provides a radio port controller in a wireless personal communications system including a first interface module in communication with a radio port, a second interface in communication with a digital switch, and at least one switching transcoder module in communication with the first and second interface modules. A further preferred embodiment provides that the switching transcoder module includes a digital signal processor. The radio port controller preferably has a communication backplane including a plurality of slots, and each slot is preferably adapted to selectively receive either a T1 card interfacing to a T1 line or an E1 card interfacing to an E1 line.

Abstract: A digital input/output circuit board includes a plurality of circuits each having an input module and an output module for mounting either an input module or an output module, wiring terminals for attaching field wires to electrically connect the circuit board to field devices, a hot wiring terminal for attaching a hot power wire, and a neutral wiring terminal for attaching a neutral power wire. A computer connected to the circuit board receives input signals indicating the state of the field devices and sends output signals to activate other field devices.

Abstract: An integrated circuit has a central processing unit for performing predetermined processing, and a communication circuit for performing data communication between the central processing unit and the outside of the integrated circuit. The communication circuit includes a data receiving unit for receiving items of data from a received signal at a time according to a given timing signal. The communication circuit also includes a time differing unit for providing a different time at which the data receiving unit receives the plural items of data from the received signal. The communication circuit also includes a selecting unit for selecting whether the time differing unit is used or not used and another selecting unit for selecting whether the given timing signal is supplied from the outside of the integrated circuit or is supplied by an internal pulse generating circuit provided in the integrated circuit.