Abstract: A limiter circuit includes a rectification circuit coupled to an input of the limiter circuit. The rectification circuit produces a voltage having a predetermined average level. The level is a function of an input signal fed to the input of the limiter circuit. A voltage divider circuit is coupled to the rectification circuit for producing an output voltage having a level proportional to the input signal. An enhancement mode field effect transistor has a gate electrode fed by the output voltage produced by the voltage divider circuit. The transistor has drain and source electrodes coupled to an output of the limiter circuit and a reference potential, respectively. A transmission line is coupled between the input of the limiter and the output of the limiter circuit. The transmission line has an electrical length n&lgr;/4, where &lgr; is the nominal operating wavelength of the limiter circuit and n is an odd integer.

Abstract: A feedforward amplifier includes a main amplifier for amplifying an input signal, a control circuit for generating a predetermined pilot signal based on the output of a local oscillator and a frequency divider included in the control circuit, and a coupler for combining the input signal or the amplified signal with the pilot signal to generate a combined signal. A first coupler and a second coupler are provided for extracting any distortion component from the combined signal. A vector adjuster, an error amplifier, and a third coupler are provided for removing the extracted distortion component from the combined signal to generate an output signal. An orthogonal detector is provided for using any one of the pilot signal, or the output of the local oscillator, the frequency divider, and the combination of the vector adjuster, error amplifier, and the third coupler to make an adjustment for removing the distortion component.

Abstract: In a power supply device including a full-wave rectifying and smoothing circuit powered from a commercial AC power supply via two power supply lines, a switching regulator for separating and stepping down the output from the full-wave rectifying and smoothing circuit to output a desired DC voltage, and two capacitors after the full-wave rectifying and smoothing circuit for the terminal noise suppression purpose, a zero-cross detection circuit includes a transistor of which the emitter is connected to the low-voltage output terminal of the full-wave rectifying and smoothing circuit for outputting a zero-cross detection signal from the collector; a first resistor is connected between the base and emitter of the transistor; a second resistor is connected between one of the power supply lines and the base of the transistor; and a third resistor is connected between the other power supply line and the emitter of the transistor.

Abstract: A synchronizing apparatus is provided in a high frequency system. The synchronizing apparatus includes a loop control circuit, a voltage controlled oscillator coupled to the loop control circuit, a matched current amplifier coupled to the voltage controlled oscillator, and a duty cycle control buffer connect to the matched circuit amplifier.

Abstract: A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node.