Patents Examined by Do Hum Yoo
  • Patent number: 5268867
    Abstract: The present invention provides a semiconductor memory device capable of reducing its current consumption, controlling the generation of noise, and increasing in access using a precharge voltage applied to a precharge circuit. In the semiconductor memory device, a precharge circuit is connected to a pair of data input/output lines, and includes a MOS transistor connected between one of the data input/output lines and a node of a precharge voltage and a MOS transistor connected between the other data input/output line and a node of the precharge voltage. The gates of the MOS transistors are supplied with control signals so that the MOS transistors are turned on when the data input/output lines are precharged. A MOS transistor is connected to the data input/output lines for equalizing them. The precharge voltage is set to half of a value obtained by subtracting the threshold voltage of the MOS transistor from the power supply voltage.
    Type: Grant
    Filed: October 6, 1992
    Date of Patent: December 7, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Momodomi, Yasuo Itoh, Yoshihisa Iwata, Tomoharu Tanaka, Yoshiyuki Tanaka
  • Patent number: 5182495
    Abstract: In a plasma processing apparatus using ECR, faces in contact with plasma excepting a substance to be processed are covered by an insulating material. By such configuration, discharge caused between the plasma and the substance to be processed in plasma processing is prevented beforehand.
    Type: Grant
    Filed: November 29, 1990
    Date of Patent: January 26, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Fukuda, Michio Ohue, Tadasi Sonobe
  • Patent number: 5180936
    Abstract: An improved GaAs switching device is disclosed, of the type having a switched clamp which shunts pull-up current except during a portion of a "0" to "1" transistion at the device's output. The device herein provided enhanced immunity to interconnect resistance by isolating the gate-to-source Schottky diode of the clamp's FET from the device's output node. In accordance with the invention, the gate-to-source current through the clamp's FET is limited by an impedance device in the FET's gate circuit to provide the isolation.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: January 19, 1993
    Assignee: Vitesse Semiconductor Corp.
    Inventor: James McDonald