Abstract: A method and system for performing write-through store operations of valid data of varying sizes in a data processing system, where the data processing system includes multiple processors that are coupled to an interconnect through a memory hierarchy, where the memory hierarchy includes multiple levels of cache, where at least one lower level of cache of the multiple of levels of cache requires store operations of all valid data of at least a predetermined size. First, it is determined whether or not a write-through store operation is a cache hit in a higher level of cache of the multiple levels of cache. In response to a determination that cache hit has occurred in the higher level of cache, the write-through store operation is merged with data read from the higher level of cache to provide a merged write-through operation of all valid data of at least the predetermined size to a lower level of cache.

Abstract: Disclosed is a system for handling recall requests for data maintained in storage devices from a host system. The host system maintains a queue of recall requests to a plurality of storage devices. Priority data is associated with each recall request in the queue. The host system initiates a recall operation for a recall request in the queue to a first storage device mounted in a drive. The host system then determines whether a next recall request to the first storage device has a higher priority than a recall request to a second storage device not mounted in a drive. The recall operation for the next recall request to the first storage device is performed after determining that the next recall request has the higher priority. The first storage device is demounted from the drive after determining that the recall request to the second storage device has the higher priority. The second storage device to the drive is mounted after demounting the first storage device from the drive.

Abstract: When memory size is increased by a factor of 2N (where N is an integer equal to or greater than unity) in a protocol-based memory system where a memory controller and multiple bus interfaces are interconnected via a bus, there exists a mismatch of N bits between the address format of each bus interface and that of the memory controller. In an initialization method for the memory system, one of the bus interfaces is enabled and request packets are transmitted successively from the memory controller to the enabled bus interface. Each packet contains a unique device identifier for identifying each bus interface. The packets of successive 2N arrivals are received at the enabled bus interface and an identifier for this bus interface is established using the device identifier contained in a predetermined one of the received packets by ignoring one or more device identifiers contained in other 2N−1 received packets.

Abstract: A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus.

Abstract: An apparatus and method for transferring a block of data between a first storage area in a first, unpacked format and a second, narrower storage area in a second, packed format. The present invention includes a set of working registers to temporarily store and manipulate portions of the block of data as it is transferred between the first and second storage areas. By employing this set of working registers, the present invention transfers blocks of data between the first and second storage areas with a low latency and the highest possible throughput.

Abstract: The present invention pertains to an apparatus for and method of mapping texture memory to a texture cache such that cache contention is minimized. Significantly, in one embodiment of the present invention, addresses of the texture memory are mapped to entries of the texture cache according to a predetermined hashing scheme. According to the one embodiment, texture memory is addressed as a virtually contiguous address space by a multi-dimensional index. The multi-dimensional index is further partitioned into a low order bit field and a high order bit field. Low order bits of the multi-dimensional index are directly mapped to low order bits of the cache address. High order bits of the multi-dimensional index are mapped to high order bits of the cache address according to a predetermined address-hashing scheme. Particularly, in one embodiment, high order bits of the multi-dimensional index are selectively “exclusive-or-ed” to generate corresponding addresses of the texture cache.

Abstract: A digital computer system comprises a mass storage subsystem and an “open systems” computer system. The mass storage subsystem includes a storage device for storing data and an access control for performing an access operation in connection with the storage device in response to a channel program received thereby in at least one channel program information transfer packet. The channel program includes at least one channel command and the supplementary channel command processing information useful in processing the at least one channel command. The “open systems” computer system performs processing operations in response to programs.

Abstract: A cache line index for an address cache entry is calculated by organizing an address such as a Media Access Control (“MAC”) address into a plurality of intermediate elements, barrel shifting the bits of at least one of the intermediate elements in accordance with predetermined criteria, and folding the intermediate address elements together with an exclusive-OR function. A Virtual Local Area Network (“VLAN”) index may also be included in cache line index calculation. The VLAN index enables segmentation of the cache into virtual tables. The tag portion of the cache entry includes a subset of the complete set of intermediate elements. The intermediate elements in the cache entry can be employed in conjunction with the cache line index to recover the original MAC address. Hence, the size of the tag portion of the address cache entry is reduced relative to the full MAC address without a reduction in the information content of the entry.

Abstract: A method, apparatus and frame format for allowing the conclusive determination of whether the devices are connected correctly is disclosed. The invention sends a first configuration message to a library manager from a device, the first configuration message including a device address and a serial number associated with the device address, forwards to a control unit from a library manager a second configuration message, the second configuration message including position information for the device and a serial number associated with the device, forwards to the control unit from the device a third configuration message, the third configuration message including position information for the device and a serial number associated with the device and compares at the control unit the second and third configuration messages to determine whether the device and the library manager are configured correctly.

Abstract: A test driver for use in validating an electronic circuit design is disclosed. The test driver not only provides stimulus and verifies the response of a circuit design, but also responds appropriately to requests provided by the circuit design. The test driver may also modify a selected portion of a data element before returning the data element to the circuit design. Under some test conditions, this helps verify that the test driver did in fact gain access to a data element during a particular test case.

Abstract: The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a microprocessor instruction, such as a CISC instruction, or the like. This increases performance by bypassing the fetch/decode pipeline stages on the front end of the microprocessor by using a parcel cache to store previously decoded instructions. The parcel cache is coupled to the microprocessor fetch/decode unit and can be searched during an instruction fetch cycle. This search of the parcel cache will occur in parallel with the search of the microprocessor instruction cache. When parcel(s) corresponding to the complex instruction being fetched are found in the parcel cache a hit occurs and the corresponding micro-ops are then sent to the execution units, bypassing the previous pipeline stages.

Abstract: A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.

Abstract: An apparatus and method are provided for detecting physical memory connected to a memory slot of a computer. The amount of physical memory within each bank is determined during boot up of the computer. Specifically, an extended physical address range exceeding 232 bytes can be accessed and, therefore, detected from boot up code contained within a ROM. The ROM contains translation tables which allow a 32 bit linear address to be translated to a physical address which can reside at boundary address locations of the fill extended physical address range. Each boundary location can be tested by writing to and reading from the specific boundary addresses to determine if physical memory is present within a sector in which the boundary address page resides. The sectors are equally spaced across the physical address range so that boot up can detect physical memory sequentially along the sector boundaries, either beginning with the lowest addressable sector or beginning at the highest addressable sector.

Abstract: A cache memory includes a data array and a trace victim cache. The data array is adapted to store a plurality of trace segments. Each trace segment includes at least one trace segment member. The trace victim cache is adapted to store plurality of entries. Each entry includes a replaced trace segment member selected for replacement from one of the plurality of trace segments.

Abstract: A tag array includes, corresponding to each line, backward and forward links for holding line numbers for storing adjacent data included in continuous data. For storing the continuous data in the tag array and a data array, backward and forward links are generated by holding beforehand storing line numbers used immediately before. For reading the continuous data from the tag array and the data array, by holding beforehand the content of a forward link in a line accessed immediately before, a number of a line for storing next data in the continuous data is specified without indexing a cache memory.

Abstract: The present invention discloses a method and system for providing defect management of a bulk data storage media wherein logical addresses of media data blocks are continuously slipped to omit all media data blocks determined to be defective at the time of an initial media format. Thereafter, selectable parameters are utilized to define a logical zone including both a user data area and corresponding replacement data area on the media such that proper selection of the parameters provides defect management optimized for a particular use of the media.

Abstract: The present invention relates to a method and apparatus for restoring a status data in a computer system.

Abstract: A method and apparatus are disclosed for sanitization of a fixed storage device interfaced to a computer system. The computer system is booted from a removable storage device that holds a bootable disk operating system and program code that is executed within the disk operating system. The fixed storage device is detected. The writeable space of the fixed storage device is then overwritten with a plurality of overwrite layers. Further, a report can be printed listing information about the sanitization process contemporaneously upon the completion of sanitization. In one embodiment, sanitizing is accomplished using a plurality of patterns, each layer having an associated pattern, to ensure that data can not be recovered even by destructive analysis.

Abstract: A cache memory system having a cache and a cache tag. A cache tag cache is provided to store a subset of the most recently or frequently used cache tags. The cache tag cache is accessed during tag inquires in a manner similar to conventional cache tag inquires. Hits in the cache tag cache have a lower access latency than the tag lookups that miss and require access to the cache tag.

Abstract: A method and apparatus for extending an on-chip processing device's access to memory are accomplished by depositing a processing circuit, memory, and configuration circuitry on a die. When the memory has sufficient digital storage capabilities for the processing circuit, the configuration circuitry directly couples an address bus and data bus between the memory and the processing device. When the memory does not have sufficient digital storage capabilities for the processing circuit, the configuration circuitry reconfigures the memory. In additional, the configuration circuitry extends the address bus to an external memory and combines the internal data bus with an external data bus. Configured in this manner, the processing device can access both the on-chip memory and the external memory as a single addressable memory, thereby increasing the memory available to the processing circuit.