Abstract: A heterojunction field effect transistor according to the invention, comprises: first, second and third semiconductor layers which are sequentially stacked on each other; a first heterojunction formed between said first and second semiconductor layers; a second heterojunction formed between the second and third semiconductor layers; first and second two-dimensional electron gas layers formed in portions of the second semiconductor layer adjacent respectively to the first and second heterojunctions; and a gate electrode, a source electrode and a drain electrode formed on either of the first and third semidconductor layers, wherein the first two-dimensional electron gas layer extends from a portion corresponding to the gate electrode to the drain electrode and has one end virtually connected to the drain electrode, the second two-dimensional electron gas layer extends from a portion corresponding to the gate electrode to the source electrode and has one end virtually connected to the source electrode, and the n

Abstract: A complimentary output pair (10) having a P-channel transistor (12) and an N-channel transistor (14) prevents output voltage spikes due to rapid changes in current with respect to time at the V.sub.cc power supply and ground (32) nodes by using a "graded turn-on." Both the P-channel transistor (12) and the N-channel (14) utilize a serpentine polysilicon gate (16), (24), in order to sequentially turn on the sub-transistors in response to a changing input. Pull-up (36) and pull-down (40) transistors are used to turn the sub-transistors (21a-j, 29a-f) off simultaneously.

Abstract: A high-speed semiconductor device including an emitter layer a base layer a collector layer, a potential-barrier layer disposed between the base layer and the collector layer, and a superlattice disposed between the emitter layer and the base layer. The superlattice has at least one quantum well therein and has a low impedance state for tunneling carriers therethrough. Preferably, the high-speed semiconductor device may further include a graded layer disposed between the emitter layer and the superlattice. The graded layer has a conduction-energy level which is approximately equal to that of the emitter layer at the interface of the graded layer and the emitter layer and approximately equal to a predetermined conduction-energy level of the superlattice at the interface of the graded layer and the superlattice. In addition, the high-speed semiconductor device may act as a frequency multiplier, providing an output signal having 2.sup.

Abstract: A differential amplifier operated as a voltage comparator includes first and second transistors coupled to first and second inputs respectively of the comparator whereby an applied input signal produces output transitions at an output of the differential amplifier as the input signal passes through and exceeds a first threshold voltage established at the second input of the differential amplifier. A hysteresis producing circuit is coupled to the differential amplifier which is responsive to the applied input signal exceeding the first threshold voltage for establishing a second threshold voltage, which is less than the first threshold voltage, whereby the input signal has to decrease below the value of the first threshold voltage to the second threshold voltage in order for the differential amplifier to switch back to its original operating state wherein hysteresis is established.