Abstract: An apparatus and method are provided that enable system designers to have programmable minimum memory page sizes. The apparatus has a memory management unit (MMU) for storing a plurality of page table entries (PTEs) and a pagegrain register for prescribing a minimum page size. Each of the PTEs in the MMU specifies a page granularity for a corresponding physical memory page, where the page granularity is bounded by the minimum page size. The MMU has and page granularity logic. The page granularity logic determines a page size for the corresponding physical memory page. The page size is determined based on the minimum page size and the page granularity. The pagegrain register prescribes the minimum page size, in default, according to a legacy memory management protocol, and in alternative, as one of the programmable minimum memory page sizes according to an extended memory management protocol.

Abstract: Disclosed is an apparatus, a system, a computer readable media, and a method for protecting data of a computer system. The method includes: (a) connecting a peripheral storage device to the computer system; (b) preparing a storage media of the peripheral storage device to be a protection enabled media; (c) selecting a backup set of data stored in a hard drive of the computer system, the backup set of data includes a default set of boot files and operating system files; (d) creating a spare tire backup using file-based copying from the hard-drive of the computer system to the storage media of the peripheral storage device; (e) enabling the peripheral storage device to incrementally copy portions of the backup set of data from the hard drive of the computer system during normal use; and (f) booting the computer system from the peripheral storage device when a failure occurs with the hard drive that disables normal booting.

Abstract: Apparatus and methods which allow multiple storage controllers sharing access to common data storage devices in a data storage subsystem to access a centralized intelligent cache. The intelligent central cache provides substantial processing for storage management functions. In particular, the central cache of the present invention performs RAID management functions on behalf of the plurality of storage controllers including, for example, redundancy information (parity) generation and checking as well as RAID geometry (striping) management. The plurality of storage controllers (also referred to herein as RAID controllers) transmit cache requests to the central cache controller. The central cache controller performs all operations related to storing supplied data in cache memory as well as posting such cached data to the storage array as required.

Abstract: A merged memory logic (MML) integrated circuit includes an adjustable clock generator configured to receive a input clock signal and produce an adjustably delayed clock signal therefrom responsively to a control signal generated by a programmable logic circuit. A buffer has a clock input for receiving the adjustably delayed clock signal and is configured to receive an input data signal and produce a corresponding output data signal therefrom responsive to the adjustably delayed clock signal. The adjustable clock generator preferably includes a clock generator configured to receive the input clock signal and produce a output clock signal therefrom, and an adjustable delay circuit which receives the output clock signal and generates the adjustably delayed clock signal therefrom, the adjustably delayed clock signal being delayed by a selected one of a plurality of selectable delay intervals with respect to the output clock signal.

Abstract: An integrated circuit memory device is designed to perform high speed burst access read and write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. The memory device maintains compatibility with nonburst mode devices such as Extended Data Out (EDO) and Fast Page Mode through bond option or mode selection circuitry. A multiplexer selects between the input address and the burst address generator output to feed an asynchronous address transition detection circuit.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: A plurality of memory cells arrayed in columns with the memory cells within a column connected between precharged first and second output lines. An input line selects a memory cell within a volume causing the first output line to be pulled to a first voltage when the cell is programmed a true and causing the second output line to be pulled to a first voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column causes the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when the cell is programmed a "complement".

Abstract: Disclosed herein is a halogen-lamp illumination/control circuit which includes a switching circuit unit for applying an a.c. power to the halogen lamp each time a firing pulse is received, a zero-crossing detection unit for detecting the timing at the time of zero-crossing of the a.c. power, a firing control unit for outputting a firing pulse each time a zero-crossing detection signal is received, and an illuminating command unit for supplying the firing pulse to the switching circuit unit during a period in which an illuminating command signal is inputted so as to make the same conductive.