Abstract: The invention provides a FET by forming a channel layer in layer including "n" type impurity at high concentration, which is sandwiched by a first semiconductor layer and a second semiconductor layer lightly doped with impurity. Therefore even when electrons in the channel layer obtain high energy, the electrons in this arrangement rush out essentially to the second semiconductor layer excelling in electron carrying characteristic, thus a travelling speed of the electrons in the channel layer is not lowered. Furthermore the channel layer being formed in layer and allowed to include impurity at high concentration, the current drive capability can be improved.

Abstract: A high voltage, high speed Schottky diode has an electrode of aluminum or like Schottky barrier metal formed on a semiconductor region to create a Schottky barrier therebetween. Also formed on the semiconductor region is a extremely thin resistive layer of, typically, oxidized titanium surrounding the barrier metal electrode and electrically connected thereto. The resistive layer also creates a Schottky barrier at its interface with the semiconductor region and serves to expand the depletion region due to the barrier metal electrode, thereby preventing the concentration of the electric field at the periphery of the barrier metal electrode and so enhancing the voltage withstanding capability of the diode.

Abstract: In a plastic encapsulated semiconductor device, a part of wire piece may break down due to thermal fatigue, which positioned adjacent to a bonding portion of the wire piece connected to a chip. This is caused by that wire piece moves relative to plastic encapsulating the chip and the wire piece, and a strain in the wire piece due to thermal deformation of the device concentrates on one portion of the wire piece. Accordingly, a rugged portion is formed on a surface of a part of wire piece subjected to a breakdown to thermal fatigue. The plastic bites recesses of the rugged portion to prevent the wire piece from moving relative to the plastic, thereby preventing the wire piece from breaking down due to thermal fatigue.

Abstract: A semiconductor device sealed with resin is disclosed. This semiconductor device comprises a semiconductor element, a lead, and a wire electrically connecting said semiconductor element and said lead. The semiconductor element, the wire, and a portion of the lead are sealed with sealing resin. Calcium hydroxide is added into the sealing resin to serve as a corrosion inhibitor. In the semiconductor device sealed with resin, corrosion of the copper wire can thus be suppressed in high temperature environments.

Abstract: A contact type image sensor comprising a transparent substrate, a non-transparent stop layer formed on the transparent substrate and having first windows, an insulator layer formed on the stop layer, a first electrode formed on the insulator layer and having second windows located at positions corresponding to positions of the first windows, a row of photoelectric conversion elements formed on the first electrode and having first and second ends, where each of the first window and the second window are provided in correspondence with one of the photoelectric conversion elements, a transparent second electrode formed on the photoelectric conversion elements, and one or a plurality of dummy windows provided at both the first and second ends of the row of photoelectric conversion elements so that each dummy window is constituted by corresponding windows formed in the stop layer and the first electrode.

Abstract: The memory matrix comprises parallel and alternating source and drain lines, floating gate areas placed between the source and drain lines and control gate lines parallel to each other and perpendicular to the source and drain lines superimposed on the floating gate areas. The floating gate areas are arranged in rows parallel to the source and drain lines in positions longitudinally staggered in relation to those of the adjacent row in such a manner that the floating gate areas of one row underlie a first plurality of control gate lines and the floating gate areas of the adjacent row underlie a second plurality alternating with the first of the control gate lines. The floating gate areas together with the adjacent source and drain lines and with the superimposed control gate lines define respective EPROM cells arranged in a staggered manner in the memory matrix.

Abstract: There is disclosed a liquid cooled high power semi-conductor structure comprising multiple stacked semi-conductor devices each having at least one surface prepared with a heat transfer surface having a low thermal resistance whereby heat generated in said semi-conductor device may be readily transported through said opposing heat transfer surface to a liquid coolant, there further being a conduit for the directing of the flow of said coolant, there being multiple semi-conductor devices stacked with heat exchange surfaces of adjacent or semi-conductor devices opposing each other, said heat exchange surfaces being spaced apart to form a coolant conduit, the several coolant conduits being fed coolant in parallel by a common input conduit and the discharge coolant feeding in parallel into a common discharge conduit, said stacked semi-conductor devices being electrically connected in series or some combination of series parallel.

Abstract: A static induction type semiconductor device is used as a power transistor. It is of the surface gate type and is used for providing a high current density. The static induction type semiconductor device provides a plurality of small source regions surrounded by a gate region. According to this structure, the channel region beneath the source region becomes small, thereby increasing the stored carrier density and enabling a large main current to flow when using a small gate current, thereby achieving a high current amplification ratio. Further, when it flows the main current is distributed to the source regions, thus preventing increase in on-voltage.

Abstract: A metal-semiconductor field effect transistor device has an active layer formed on a first main surface of a semiconductor substrate with a first gate electrode provided on the active layer in Schottky contact therewith and source and drain electrodes provided on opposite sides of the first gate electrode and in ohmic contact with the active layer so as to define corresponding source and drain regions in the active layer with an active region of the active layer extending therebetween. A second gate electrode including first and second portions is provided in Schottky contact on the active layer, respectively on the exposed surface portion segments thereof intermediate the opposite sides of the first gate electrode and the respective drain and source electrodes associated with the first gate electrode.

Abstract: A quantum diffraction field effect transistor ("QUADFET"), a new class of semiconductors which exploits the phenomenon of electron diffraction to produce novel circuit characteristics.

Abstract: A turn-on/off driving technique for an insulated gate thyristor which has a first gate electrode insulatively provided above a first base layer and fuctioning as a gate of MOSFET, and a second gate electrode formed on the second base layer. To drive the turn-on of the thyristor, a first voltage for rendering the MOSFET conductive is applied to the first gate electrode, while substantially simultaneously a second voltage for producing forward biasing between the second base layer and a second emitter layer is applied to the second gate electrode. To turn-off drive the thyristor, a third voltage for reverse biasing between the second emitter layer and the second base layer to stop the operation of the thyristor is applied to the second gate, while the MOSFET is kept conductive. The thyristor starts turning off in response to the voltage application.

Abstract: In a metal-ceramic housing for a high-power GTO, a space-saving auxiliary cathode connection (5a) capable of carrying current is achieved in that it is constructed by embedding in the insulating ring (4) of the housing and is connected directly to the cathode contact plate (9) via its own connecting elements (11, 13, 15).

Abstract: A complementary bipolar transistor structure having one symmetrical intrinsic region for both the NPN and PNP transistors and a method for fabricating the structure. The transistor structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. In the method, the sub-emitter and the sub-collector regions are formed by depositing a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, and forming the sub-collector by etching a shallow trench in the first layer and depositing semiconductor material of a second conductivity type by LTE and planarizing.