Patents Examined by Donald J. Featherstone
  • Patent number: 4841345
    Abstract: A planar vertical diffusion self aligned conductivity modulated MOSFET comprising a semiconductor island region (70) of a first conductivity type having a high impurity concentration and formed in an island shape in a predetermined region on the surface on the side of a electrode (8) of a semiconductor substrate layer (10) of a second conductivity type having a high impurity concentration.
    Type: Grant
    Filed: August 26, 1986
    Date of Patent: June 20, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Gourab Majumdar
  • Patent number: 4827323
    Abstract: The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates.
    Type: Grant
    Filed: May 12, 1988
    Date of Patent: May 2, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Howard L. Tigelaar, Bert R. Riemenschneider
  • Patent number: 4819043
    Abstract: An MOSFET provided with a gate insulating film formed on a semiconductor surface between a source region and a drain region, a gate electrode formed on the gate insulating film, and a channel region sandwiched between the source region and the drain region and made up of a first layer and a second layer is disclosed in which the first layer lies beneath the gate insulating film and is opposite in conductivity type to the source and drain regions, the second layer lies beneath the first layer and has the same conductivity type as the source and drain regions, and the length of the second layer between the source region and the drain region is greater than the length of the first layer between the source region and the drain region.
    Type: Grant
    Filed: December 1, 1986
    Date of Patent: April 4, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiaki Yazawa, Yutaka Kobayashi, Akira Fukami, Takahiro Nagano
  • Patent number: 4816894
    Abstract: A variable capacitive element is comprised of a semiconductor substrate having a major surface and a capacitive region under the major surface of the semiconductor substrate, a floating electrode disposed on and electrically insulated from the semiconductor substrate through an insulating film for storing electric charge to build up an electric potential in the floating electrode according to the stored amount of electric charge to thereby determine an amount of capacitance of the capacitive region, and a control electrode for injecting electric charge into the floating electrode. A terminal electrode is electrically connected to the capacitive region for electrically connecting the capacitive region to an external circuit. The terminal electrode is capacitively coupled to the floating electrode. A given voltage is applied to the terminal electrode to adjust the electric potential of the floating electrode through the capacitive coupling between the terminal electrode and floating electrode.
    Type: Grant
    Filed: January 29, 1987
    Date of Patent: March 28, 1989
    Assignee: Seiko Instruments & Electronics Ltd.
    Inventor: Yoshio Hattori
  • Patent number: 4810906
    Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N- layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.
    Type: Grant
    Filed: April 22, 1988
    Date of Patent: March 7, 1989
    Assignee: Texas Instruments Inc.
    Inventors: Ashwin H. Shah, Pallab K. Chatterjee
  • Patent number: 4811069
    Abstract: A photoelectric conversion device comprises a photodiode comprising a metallic electrode formed of a metal capable of forming a Schottky junction together with amorphous silicon, such as Cr or Ni, a transparent electrode formed of ITO or the like, and an i-type hydrogenated amorphous silicon layer sandwiched in between the metallic electrode and the transparent electrode. A bias voltage is applied across the metallic electrode and the transparent electrode so that the metallic electrode is biased to a negative potential relative to the transparent electrode. A Schottky barrier formed in the interface between the metallic electrode and the i-type hydrogenated amorphous silicon layer is used as an electron blocking layer. Thus, the dark current is suppressed on a low level and the photoelectric conversion device is able to operate at a high S/N ratio.
    Type: Grant
    Filed: February 22, 1988
    Date of Patent: March 7, 1989
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroaki Kakinuma, Yukio Kasuya, Masaaki Sakamoto, Tsukasa Watanabe
  • Patent number: 4809045
    Abstract: An insulated gate device includes at least one cell having base and emitter region surfaces disposed in ohmic contact with a metallic emitter electrode. The cell is constructed to provide a larger ratio of base region surface area to emitter region surface area in contact with the emitter electrode than is found in the prior art. The cell is further constructed to provide paths for reverse current flow from a drift region through the base region and to the emitter electrode; these paths being spaced form the cell's emitter-base junction.
    Type: Grant
    Filed: September 30, 1985
    Date of Patent: February 28, 1989
    Assignee: General Electric Company
    Inventor: Hamza Yilmaz
  • Patent number: 4801994
    Abstract: By providing an intrinsic semiconductor region in a reverse biased junction cathode between an n-type surface region and a p-type zone, a maximum field is present over the intrinsic region in the operating condition. The efficiency of the cathode is increased because avalanche multiplication can now occur over a greater distance, while in addition electrons to be emitted at a sufficient energy are generated by means of tunneling.
    Type: Grant
    Filed: March 5, 1987
    Date of Patent: January 31, 1989
    Assignee: U.S. Philips Corporation
    Inventors: Gerardus G. P. Van Gorkom, Arthur M. E. Hoeberechts
  • Patent number: 4799097
    Abstract: The structure of a pair of concentrically disposed field effect transistors responsive to a common gate electrode, and a process for the fabrication thereof. In one form, a dielectric region is surrounded by an active region of monocrystalline silicon and has situated upon the dielectric region a layer of recrystallized silicon as a second active region. A gate electrode overlies both active regions and serves as a mask to form in such respective regions self-aligned channels. The concentric placement of the active substrate monocrystalline silicon region, and inner perimeter of dielectric, and a further inner active region of recrystallized silicon situated over a dielectric region, facilitates recrystallization from seed of monocrystalline silicon irrespective of the direction of translation taken by the energy beam, and associated melt, in scanning across the structure.
    Type: Grant
    Filed: July 29, 1987
    Date of Patent: January 17, 1989
    Assignee: NCR Corporation
    Inventors: Nicholas J. Szluk, Jay T. Fukumoto
  • Patent number: 4796082
    Abstract: A thermally stable low resistance ohmic contact to gallium arsenide is fabricated using a layer of refractory material, and a layer of indium and a metal which forms thermally stable intermetallic compounds or single solid phase with indium. In forming the contact, a layer of indium is sandwiched between two layers of nickel, the sandwiched array of layers sitting on the substrate with the refractory tungsten layer on top to form a stratified structure. The stratified structure is heated to form nickel and indium intermetallic compounds and InGaAs layer at the metal/semiconductor interface. A thin layer of nickel between the indium and the gallium arsenide tends to form intermetallic compounds and limit a rate of diffusion of the indium into the gallium arsenide during heating so as to form a uniform fine distribution of InGaAs layer at the metal/gallium arsenide interface which results in low contact resistance. A contact resistance of 0.
    Type: Grant
    Filed: March 16, 1987
    Date of Patent: January 3, 1989
    Assignee: International Business Machines Corporation
    Inventors: Masanori Murakami, William H. Price
  • Patent number: 4794438
    Abstract: A semiconductor radiation detector having a body which includes a matrix of semiconductor material, specifically silicon, having an array of individual rods of conductive material, specifically TaSi.sub.2, disposed therein. The rods form Schottky barriers with the semiconductor material. A set of contacts spaced along the length of the body each make ohmic contact to several rods at one end of each rod, and an ohmic contact is made to the semiconductor material of the matrix. Incident radiation is directed at a surface of the body which lies parallel to the rods. Detectors connected to each of the contacts along the length of the body detect current flow generated in the vicinity of the rods associated with each contact member by radiation penetrating into the body to that depth.
    Type: Grant
    Filed: March 16, 1987
    Date of Patent: December 27, 1988
    Assignee: GTE Laboratories Incorporated
    Inventors: Mark Levinson, Ben G. Yacobi, Brian M. Ditchek
  • Patent number: 4794432
    Abstract: A disclosed MOSFET cell has a source region formed at the top surface of a semiconductor substrate. The top surface source region is electrically coupled to a conductive region at a bottom portion of the substrate by means of a vertical conduit which projects through the substrate from the top surface to the conductive region. A current exchanger is provided extending over the top surface of the substrate and coupling a top surface portion of the vertical conduit to the source region. The current exchanger makes ohmic contact with the source region and with the conduit region and shorts the two regions together such that majority carrier current of the conduit region will be "converted" into majority carrier current of the source region and electrical continuity between the source region and the conductive region of the substrate is established.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: December 27, 1988
    Assignee: General Electric Company
    Inventors: Hamza Yilmaz, King Owyang, Robert G. Hodgins
  • Patent number: 4789887
    Abstract: A voltage controlled oscillator includes a VCO chip that is a monolithic circuit with a Gunn diode and varactor diode intercoupled by a resonant circuit. A detector/discriminator/power divider chip is coupled to the VCO chip through a directional coupler and is a monolithic circuit having a pair of discriminator diodes and amplitude detector diode on a semi-insulating substrate with associated circuit components. Connected-together electrodes of the discriminator diodes are connected to one output of the power divider. An electrode of the amplitude detector diode is connected to the other output of the power divider. Stagger-tuned resonant circuits are coupled to the other electrodes of the discriminator diodes. Conducting portions forming low pass filters couple the amplitude detector diode and the discriminator detector diodes to respective outputs.
    Type: Grant
    Filed: September 29, 1986
    Date of Patent: December 6, 1988
    Assignee: Alpha Industries, Inc.
    Inventors: Ian Crossley, Daniel Donoghue, Robert Goldwasser, John Miley, Frank Spooner
  • Patent number: 4789886
    Abstract: A high voltage semiconductor includes an electrically floating conductive layer located adjacent the field oxide in the gap region between a junction pair. The electrically floating conductive layer allows free charge in the insulating layers to be dissipated. As a result, the depletion region in the substrate is extended and the breakdown voltage of the device is improved considerably.
    Type: Grant
    Filed: January 20, 1987
    Date of Patent: December 6, 1988
    Assignee: General Instrument Corporation
    Inventor: Douglas A. Pike, Jr.
  • Patent number: 4788579
    Abstract: A semiconductor device comprises two layers of semiconductor material each of different conductivity type, with a region of semiconductor material sandwiched between the layers. The material of which the region is formed is of the same composition as the first layer at the edge of the region adjacent to the first layer, and varies in composition linearly on the running average in the direction between the layers such that the region forms a heterojunction with the second layer.
    Type: Grant
    Filed: September 15, 1986
    Date of Patent: November 29, 1988
    Assignee: The General Electric Company
    Inventors: Nigel R. Couch, Michael J. Kelly
  • Patent number: 4786955
    Abstract: A semiconductor device having a layer of semiconductor material disposed on an insulating substrate is disclosed. Source and drain depth extenders are provided within the semiconductor material for extending the respective source and drain regions to the insulating substrate. This device is fabricated in a manner which minimizes damage to the gate oxide layer that often occurs when high energy implants are used to form self-aligned source and drain regions.
    Type: Grant
    Filed: February 24, 1987
    Date of Patent: November 22, 1988
    Assignee: General Electric Company
    Inventors: Dora Plus, Ronald K. Smeltzer
  • Patent number: 4775879
    Abstract: A vertical field effect transistor is provided which has its sources arranged in a pattern to essentially eliminate inactive common drain area between the sources. The preferred arrangement is to use rectangular source areas to form columns and rows in the arrangement. Every other row is shifted so that a source in a shifted row is positioned between sources in an adjacent row. The rows are then spaced closer together thereby achieving the substantial elimination of inactive drain area. The elimination of inactive drain area results in low on resistance during the conductive state of the vertical field effect transistor.
    Type: Grant
    Filed: March 18, 1987
    Date of Patent: October 4, 1988
    Assignee: Motorola Inc.
    Inventors: Stephen P. Robb, Lewis E. Terry
  • Patent number: 4766472
    Abstract: A monolithic semiconductor structure of a laser and a field effect transistor applicable to telecommunications comprises, on a semiinsulating substrate, a semiconductor layer of Ga.sub.1-x Al.sub.x As, a N-doped semiconductor layer of Ga.sub.1-y Al.sub.y As, a semiconductor layer of Ga.sub.1-z Al.sub.z As, in which x and z vary from 0.2 to 0.7 and y from 0 to 0.15 and a GaAs semiconductor layer. In these four layers are formed one type P region and two type N regions, the type P region and one of the type N regions defining between them the active zone of the laser and the two type N regions defining between them the active zone of the transistor, respectively forming the transistor source and drain. The P region of the laser is equipped with an electrode and the transistor source and drain with ohmic contacts. A process for making the structure as also disclosed.
    Type: Grant
    Filed: January 5, 1987
    Date of Patent: August 23, 1988
    Inventors: Francois Brillouet, Krishna Rao, Francois Alexandre
  • Patent number: 4764802
    Abstract: A semiconductor device comprises a drain region, base regions, gate electrodes formed over the drain region between two adjacent base regions through an insulating layer such that each bridges the surface of the drain region to partially cover the two adjacent base regions, source regions provided in the base regions, a source electrode provided on the source regions, and a metal gate electrode wiring contacting the gate electrodes. The metal gate electrode wiring includes closed loop portions and the source electrode is divided into branch sections, each corresponding to the closed loop portion.
    Type: Grant
    Filed: February 12, 1987
    Date of Patent: August 16, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masashi Kuwahara
  • Patent number: 4764796
    Abstract: A field effect transistor utilizing semiconductor hetero junction having a high mutual conductance, low noise, and a reduced source resistance, has a gallium indium arsenide mixed crystal semiconductor layer (23) providing a current path, low resistance indium phosphide layers formed on or under the gallium indium arsenide mixed crystal semiconductor layer (23) by ion-implantation for achieving the reduced source resistance, a source electrode (6), a gate electrode (5) and a drain electrode (7) which are formed on the surface of an uppermost aluminum indium arsenide mixed crystal semiconductor layer (24), an ion-implanted layer located at least in a region to form the reduced source resistance between the source electrode (6) and a two-dimensional electron layer (8) within the gallium indium arsenide mixed crystal semiconductor layer (23).
    Type: Grant
    Filed: December 9, 1986
    Date of Patent: August 16, 1988
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Goro Sasaki, Hideki Hayashi