Abstract: An improvement to a spread-spectrum code-division-multiple-access system, using a channel sounding signal from a base station (BS) to provide initial transmitter power levels for remote stations (RS). The base station transmits BS-spread-spectrum signals at a first frequency and receives RS-spread-spectrum signals, which are transmitted by the remote stations at the second frequency. The base station transmits a BS-channel-sounding signal at the same carrier frequency being used by the remote stations. The bandwidth of the BS-channel-sounding signal is much less than the bandwidth of the BS-channel-spread-spectrum signal. Each remote station tracks the BS-channel-sounding signal, for adjusting the initial RS-power level.
Abstract: K data signals are transmitted over a shared spectrum in a code division multiple access communication system. A combined signal is received and sampled over the shared spectrum. The combined signal has the K transmitted data signals. A combined channel response matrix is produced using the codes and impulse responses of the K transmitted data signals. A block column of a combined channel correlation matrix is determined using the combined channel response matrix. Each block entry of the block column is a K by K matrix. At each frequency point k, a K by K matrix &Lgr;(k) is determined by taking the fourier transform of the block entries of the block column. An inverse of &Lgr;(k) is multiplied to a result of the fourier transform. Alternately, forward and backward substitution can be used to solve the system. An inverse fourier transform is used to recover the data from the K data signals.
Type:
Grant
Filed:
December 31, 2001
Date of Patent:
September 23, 2003
Assignee:
InterDigital Technology Corporation
Inventors:
Parthapratim De, Jung-Lin Pan, Ariela Zeira
Abstract: A converter or a resampler used in a digital communication system converts a first digital signal representing an analog signal into a second digital signal representing the same analog signal. The converter includes a converter filter and a timing circuit. The timing circuit provides a first clock generated from a second clock, and a phase control signal for controlling the conversion of the converter filter. The timing circuit is preferably a numerical controlled oscillator (NCO) and includes an accumulator for generating the first clock from the second clock and a phase offset, and a phase calculator which receives the phase offset to generate a phase control signal. The phase control signal includes a plurality of phase weighting signals, a plurality of control signals, and an interpolation signal. The first digital signal is selectively convoluted with the phase weighting signals, which is controlled by the control signals.
Type:
Grant
Filed:
June 2, 1999
Date of Patent:
June 24, 2003
Assignee:
Level One Communications, Inc.
Inventors:
John Camagna, Tein-Yow Yu, James Ward Girardeau, Jr.
Abstract: A DC offset cancellation circuit comprises a subtracter, a noise shaper, an accumulator and an attenuator. The subtracter is used to subtract a quantized DC offset from a digital signal. The noise shaper converts an unquantized DC offset into the quantized DC offset, the quantized DC offset having fewer bits than the unquantized DC offset and an average value in the time domain that is approximately equal to the unquantized DC offset. The accumulator generates an accumulation value by means of summing the outputs of the subtracter. The attenuator is employed to multiply the accumulation value by a constant, which is less than one, and transmit the resulting initial DC offset to the subtracter.
Type:
Grant
Filed:
November 18, 1998
Date of Patent:
November 27, 2001
Assignee:
Industrial Technology Research Institute