Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.

Abstract: Provided is a technique of effectively removing a metallic element that has catalytic action in terms of the crystallization of a semiconductor film and remains in a semiconductor film obtained using the metallic element. With the technique of the present invention, to remove a catalytic element used to crystallize a semiconductor film having an amorphous structure, gettering is completed by forming a region or a semiconductor film, to which a rare gas element is added, and by having the catalytic element move to the formed region or semiconductor film.

Abstract: An image sensor includes a semi-conducting substrate having a photo-sensitive region and doping for forming a path to a charge-to-voltage mechanism; a dielectric spanning the substrate; and a semi-conducting layer, which is less than approximately 1 micrometer, spanning the dielectric which contains electrodes and circuit elements that control flow of charge.

Abstract: A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory device, a device isolation layer is formed in a substrate. Gate insulating layers having difference thickness are formed in low-and high-voltage regions of the peripheral region, respectively. A first conductive layer is formed over substantially the entire surface of a gate insulating layer in the peripheral region. A triple layer including a tunneling insulating layer, a charge storage layer, and a blocking insulating layer and a second conductive layer are sequentially formed over substantially the entire surface of the substrate including the first conductive layer.

Abstract: A light-emitting device which uses and LED having a light-emitting element being placed on a package substrate. The light-emitting element has a light-extracting surface. A fluorescent element which is formed by dispersing a fluorescent material in a transparent substance and is placed face to face with the light-extracting surface of the light emitting element and comprises a clearance gap in between. The light-emitting element generates light of a certain wavelength that emanates through the light-extracting surface into the fluorescent element where the wavelength is changed. The device further comprises an optical element which receives light from the light-emitting element through the fluorescent element and directs the light to the outside of the device.

Abstract: The invention involves an array to couple a live cell, in particular a nerve cell, with an electronic circuit to pick up directly or indirectly electrically active cell signals and/or to electronically stimulate the cell, where the coupling array comprises a transistor (T1) with a double gate, where one of the gates is designed as a control gate (CG) to select the transistor via external control signals, and the other gate (FG) is connected to an electrically conducting contact element (1) which may be brought into contact with the cell (2) to register changes in the electric properties of the cell.

Abstract: An object is to provide a semiconductor device manufacturing method which makes possible a thin film transistor which is little affected by crystal grain boundaries, even when the channel width of the thin film transistor is made larger than the crystal grains of the semiconductor material. To this end, a thin film transistor of this invention comprises a gate electrode 22, source region 24, drain region 25, and channel formation region 26. The silicon film used in forming the active region comprises a plurality of substantially single-crystal silicon crystal grains, and regions including crystal grain boundaries which exist in the longitudinal direction of the channel formation region 26 (the direction L in the drawings) are removed. By this means, crystal grain boundaries are prevented from being included in each channel formation region 26, and the effective channel width can be increased.

Abstract: A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the VCC and VSS. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for high-performance, low-voltage, and low-power VLSI circuits on SOI wafers.

Abstract: A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting the channel region, a floating diffusion region formed continuous from the channel region, and an output transistor having a gate connected to the floating diffusion region. In a region where the output transistor is formed, the dopant density profile in the depth direction of the semiconductor substrate exhibits the maximum value relative to a middle region.

Abstract: A method for manufacturing light emitting diode device by mounting an LED on a substrate, providing electrodes to connect the substrate to the LED for applying a current to the LED, encapsulating the LED with an encapsulating resin, measuring chromaticity of light emitted from the encapsulated LED, calculating a correcting chromaticity necessary for correcting the measured chromaticity of the light from the encapsulated LED to a desired chromaticity, preparing filter agents for the correcting chromaticity of light from the encapsulated LED and applying the adjusted filter agents to the surface of the encapsulating resin.

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the transistor gate.

Abstract: A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seamless bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

Abstract: In a method for fabricating a semiconductor device including a PIP capacitor and a MOS transistor, an isolator film is formed on a semiconductor substrate and then etched to expose an active region of the substrate. An epitaxial film is then formed by performing a selective epitaxial silicon growth process on the active region. A first polysilicon film, a dielectric film and a second polysilicon film are then sequentially formed. Next, an upper electrode is created by patterning the second polysilicon film. After a lower electrode and a gate electrode are formed by patterning the first polysilicon film, a source and a drain of a source/drain region are formed into the epitaxial film. Subsequently, after an interlayer insulation film is created on a resultant structure, contact holes are formed thereinto and contacts connected to the upper electrode, the lower electrode, the gate electrode and the source/drain region are formed.

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: An apparatus and method for preventing damage to tape attachment semiconductor assemblies due to encapsulation filler particles causing damage to a semiconductor die active surface and/or to a corresponding semiconductor substrate surface by providing an adhesive tape which extends across areas of contact between the semiconductor die active surface and the semiconductor substrate. The present invention also includes extending the adhesive tape beyond the areas of contact between the semiconductor die active surface and the semiconductor substrate to provide a visible surface of visual inspection of proper adhesive tape placement.

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.

Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

Abstract: A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

Abstract: A device for reading an image (an image reading device) according to this invention comprises therein at least one photoelectric conversion semiconductor device provided on a substrate and at least one thin film transistor circuit element provided on the substrate wherein said photoelectric conversion semiconductor device and said thin film transistor circuit element comprise semiconductor regions obtained from one semiconductor film provided on said substrate.