Abstract: Deceleration control apparatus for an aircraft having an automatic altitude capture and hold system and an airspeed hold system, both systems controlled by controlling pitch attitude wherein during a descent from a higher altitude under airspeed-on-pitch control with throttle set at idle thrust, and at some existing negative altitude rate, a slower speed is commanded, a synthetic altitude based on the existing descent rate is computed and the attitude capture and hold system operation is switched into control in place of the airspeed on pitch control to cause the aircraft to flare toward the synthetic altitude. The resultant loss of airspeed, i.e., craft deceleration, during the altitude capture flare is monitored and when the commanded airspeed reduction is achieved, the airspeed-on-pitch control is resumed to thereby hold the commanded lower airspeed.

Abstract: An incoming serial Manchester signal is synchronously sampled by a first flip-flop with respect to a reference clock signal of a frequency f.sub.o. A second flip-flop divides the reference clock signal to provide f.sub.o /2 clocking to a pair of shift registers wherein one shift register is of bit length M and the other is of bit length N. The first flip-flop provides to the first shift register a present sample corresponding to the state of the Manchester waveform. A third flip-flop samples and stores the state of the Manchester waveform sample, as provided by the first flip-flop, which occurred one-half clock period prior to the f.sub.o /2 clocking of the shift registers. The third flip-flop provides to the second shift register a delayed sample corresponding to the state of the Manchester waveform. The sample provided to the second shift register is a sample which occurred previously in time, by 1/f.sub.o clock period, relative to the present sample provided to the first shift register.

Abstract: An automatic equalizer and oscillation suppressor system utilizing phase lock loop circuits to detect oscillation candidates at identified frequencies and a low cost microprocessor to process corrective band gain action. Oscillation candidates are initially suppressed by incremental adjustment of band gains to a maximum point after which notch filters are assigned to the oscillating frequency and the band gain returned to its normal equalized value. Automatic equalization is achieved initially with a pink noise source and on an on-going real time basis with program content by use of a frequency addressable narrow band boost circuit which is selectively inserted at frequencies across the bandwidth and band gains adjusted until some oscillation has occurred in all bands or maximum master gain has been reached.

Abstract: A simulation model is provided which comprises a combination of the physical device to be modeled and means for controlling the physical device at normal operating speeds so as to avoid loss of data or of accumulated functions. Specifically, the physical device to be modeled is connected through a micro-system simulation means which can accept any of a wide variety of external devices and which includes the logic circuitry and control means necessary to allow the physical device to be stimulated and the resulting behavior observed under external control. Data and logic state patterns are preserved by effective control of the starting, stopping, cycling and resetting of the physical device.

Abstract: A leading edge estimator for a vehicle terrain navigation system is described, the system having a radar terrain sensor which generates a position signal. The leading edge estimator includes a storage circuit for storing a time of arrival signal estimate. A delay circuit receives the position signal from the radar terrain sensor and produces a delayed version thereof. The position signal and the delayed version thereof are differenced and applied to a sample & hold circuit, which generates a sample of the differenced signal after a predetermined time period. The output of the sample & hold circuit is then applied to a one bit analog-to-digital convertor which determines the sign of the sampled difference signal. The output of the analog-to-digital convertor is then used as a control signal to effect the gating of one of two predetermined weighting factors.

Abstract: This invention concerns a method of characterizing the reliability in bipolar semiconductor devices having reliability detracting leakage current due to a parasitic FET transistor between the p-type isolation (source) and base regions (drain) of the bipolar, NPN transistor. The source of this PNP parasitic FET transistor, i.e., the isolation region and the gate are provided with electrodes and the drain region and gate electrodes short-circuited. Then, a reliability function R is determined as equal to the product N.sub.SS .times.N.sub.eff .times.N.sub.D 1/2, wherein N.sub.SS, is the interface charge density, N.sub.eff, is the oxide charge density, and N.sub.D, is the impurity concentration in the epitaxial layer. This function is correlated with the time-to-fail, such as, for instance, T.sub.50. It suffices to characterize the manufacturing line beforehand by plotting curve R=f(T.sub.