Patents Examined by Douglas W. Owens
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Patent number: 11581280Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.Type: GrantFiled: November 25, 2020Date of Patent: February 14, 2023Assignee: STMICROELECTRONICS PTE LTDInventor: David Gani
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Patent number: 11581284Abstract: A semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. A lower surface of the UBM via has a first area in contact with the UBM pad, and a second area having a step configuration relative to the first area and that extends outwardly of the first area.Type: GrantFiled: March 16, 2021Date of Patent: February 14, 2023Inventors: Myungsam Kang, Youngchan Ko, Jeongseok Kim, Kyungdon Mun
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Patent number: 11581248Abstract: A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.Type: GrantFiled: April 7, 2021Date of Patent: February 14, 2023Inventor: Aenee Jang
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Patent number: 11574861Abstract: A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.Type: GrantFiled: March 25, 2021Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11569190Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a first top surface of the semiconductor substrate; a circuit board including a second top surface, a recess indented from the second top surface into the circuit board, a polymeric pad disposed on the second top surface and corresponding to the first pad, and an active pad disposed within the recess and corresponding to the second pad; a first bump disposed between and contacting the polymeric pad and the first pad; and a second bump disposed between and contacting the active pad and the second pad, wherein a height of the first bump is substantially shorter than a height of the second bump.Type: GrantFiled: December 8, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Lin Lu, Kai-Chiang Wu
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Patent number: 11557557Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.Type: GrantFiled: June 30, 2020Date of Patent: January 17, 2023Assignee: QUALCOMM INCORPORATEDInventors: Yangyang Sun, Dongming He, Lily Zhao
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Patent number: 11557619Abstract: The incidence of incident light transmitted through a photoelectric conversion unit onto a charge holding unit, a pixel in the adjacency, and the like can be blocked in a pixel. An image sensor includes a pixel, a wiring layer, and an incident light attenuation unit. The pixel includes a photoelectric conversion unit that is formed in a semiconductor substrate and performs photoelectric conversion based on incident light, and a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion. The wiring layer is arranged on a surface of the semiconductor substrate different from a surface onto which the incident light is incident, and transports either the image signal or a signal applied to the pixel circuit. The incident light attenuation unit attenuates the incident light transmitted through the photoelectric conversion unit.Type: GrantFiled: November 2, 2018Date of Patent: January 17, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Shinichiro Noudo
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Patent number: 11557560Abstract: A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.Type: GrantFiled: April 6, 2021Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yeohoon Yoon, Hyungsun Jang
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Patent number: 11538756Abstract: A bonding structure is provided. The bonding structure includes a conductive layer, a seed layer, and a nanotwinned copper (NT-Cu) layer. The seed layer is disposed on the conductive layer. The NT-Cu layer is disposed on the seed layer. The NT-Cu layer has anisotropic crystal structure.Type: GrantFiled: September 16, 2020Date of Patent: December 27, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shun-Tsat Tu, Pei-Jen Lo, Chien-Han Chiu
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Patent number: 11538931Abstract: A semiconductor device includes a carrier generation layer disposed on a channel layer, a source contact and a drain contact disposed on the carrier generation layer, and a gate contact disposed between the source contact and the drain contact. The semiconductor device further includes a number N of conductive stripes disposed directly on the carrier generation layer in an area between the drain contact and the gate contact, and a number M of conductive transverse stripes disposed directly on the carrier generation layer in the area between the drain contact and the gate contact. Each of the N conductive stripes extends from and is electrically coupled to the drain contact. Each of the M conductive transverse stripes is aligned non-parallel to the N conductive stripes and is not in direct physical contact with the N conductive stripes.Type: GrantFiled: August 7, 2020Date of Patent: December 27, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Woochul Jeon, Ali Salih, Llewellyn Vaughan-Edmunds
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Patent number: 11532524Abstract: A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.Type: GrantFiled: March 8, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsien-Wen Liu, Hsien-Wei Chen
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Patent number: 11527498Abstract: Aspects disclosed herein include a device including a bump pad structure and methods for fabricating the same. The device includes a bump pad. The device also includes a first trace adjacent the bump pad, where a first trace top surface is recessed a first recess distance from a bump pad top surface. The device also includes a second trace adjacent the first trace, covered at least in part by a solder resist. The device also includes a substrate, where the bump pad, the first trace, and the second trace are each formed on a portion of the substrate.Type: GrantFiled: September 30, 2020Date of Patent: December 13, 2022Assignee: QUALCOMM INCORPORATEDInventors: Kuiwon Kang, Michelle Yejin Kim, Marcus Hsu
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Patent number: 11527499Abstract: An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.Type: GrantFiled: February 4, 2021Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tsui-Mei Chen, Tsung-Jen Liao, Li-Huan Chu, Pei-Haw Tsao
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Patent number: 11508691Abstract: A semiconductor structure includes a first substrate including a first contact structure located on a first pad, and a second substrate including a second contact structure on a second pad. The first contact structure includes a first metal base layer covered by a first nano-twinned metal coating layer. The second contact structure includes a second nano-twinned metal coating layer on the second pad. The first contact structure is connected to the second contact structure, thereby forming a bonding interface between the first nano-twinned metal coating layer and the second nano-twinned metal coating layer.Type: GrantFiled: March 15, 2021Date of Patent: November 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventor: Po-Yu Yang
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Patent number: 11504012Abstract: A diaphragm-based sensor includes a deflectable diaphragm, a base layer opposite the diaphragm, and a corrugated wall extending between the diaphragm and the base layer. The diaphragm is suspended over a cavity enclosed by the diaphragm, the base layer and the corrugated wall. The diaphragm includes a first electrode and the base layer includes a second electrode such that a capacitance between the first and second electrodes changes when the diaphragm is deflected relative to the cavity.Type: GrantFiled: January 22, 2020Date of Patent: November 22, 2022Assignee: University of PittsburghInventor: Sung Kwon Cho
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Patent number: 11502117Abstract: An image sensor includes a substrate having a first surface and a second surface facing each other, a plurality of photoelectric conversion regions disposed in the substrate, an isolation pattern disposed in the substrate between the photoelectric conversion regions, a conductive connection pattern disposed on the isolation pattern and in a trench penetrating the first surface of the substrate, and a first impurity region disposed in the substrate and adjacent to the first surface of the substrate. A first sidewall of the conductive connection pattern is in contact with the first impurity region. A dopant included in the conductive connection pattern includes the same element as an impurity doped in the first impurity region.Type: GrantFiled: June 12, 2020Date of Patent: November 15, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyoun-Jee Ha, Changhwa Kim
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Patent number: 11502068Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.Type: GrantFiled: March 3, 2021Date of Patent: November 15, 2022Assignee: NXP USA, INC.Inventors: Burton Jesse Carpenter, Fred T. Brauchler
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Patent number: 11498097Abstract: A piezoelectric micromachined ultrasonic transducer (PMUT) includes a substrate, a stopper, and a membrane, where the substrate and the stopper are composed of same single-crystalline material. The substrate has a cavity penetrating the substrate, and the stopper protrudes from a top surface of the substrate and surrounds the edge of the cavity. The membrane is disposed over the cavity and attached to the stopper.Type: GrantFiled: May 21, 2020Date of Patent: November 15, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Rakesh Kumar, Jia Jie Xia, You Qian
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Patent number: 11488916Abstract: A conductive structure is provided. The conductive structure includes a first conductive layer, a second conductive layer, and an insulating layer sandwiched between the first conductive layer and second conductive layer. The insulating layer has a first opening and a second opening through which the first conductive layer is electrically connected to the second conductive layer. The partition between the first opening and the second opening has a width greater than 0 and less than or equal to the average width of the first opening and second opening.Type: GrantFiled: January 12, 2021Date of Patent: November 1, 2022Assignee: Innolux CorporationInventors: Maggy Hsu, Pierre Chen
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Patent number: 11488913Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.Type: GrantFiled: September 29, 2020Date of Patent: November 1, 2022Assignee: Socionext Inc.Inventors: Akio Hara, Toyoji Sawada, Masaki Okuno, Hirosato Ochimizu