Abstract: Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises an insulating layer formed on the upper surface of a chip provided with a plurality of terminals on its one surface, a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance so as to be connected to each of a plurality of the terminals, and a plurality of electrode surfaces formed on each of the upper surfaces of a plurality of the conductive layers. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.

Abstract: An optical sensor is provided, comprising (a) a silicon nanowire of finite length having an electrical contact pad at each end thereof; and (b) a plurality of self-assembled molecules on a surface of the silicon nanowire, the molecules serving to modulate electrical conductivity of the silicon nanowire by either a reversible change in dipole moment of the molecules or by a reversible molecule-assisted electron/energy transfer from the molecules onto the silicon nanowire. Further, a method of making the optical sensor is provided. The concept of molecular self-assembly is applied in attaching functional molecules onto silicon nanowire surfaces, and the requirement of molecule modification (hydroxy group in molecules) is minimal from the point view of synthetic difficulty and compatibility. Self-assembly will produce well-ordered ultra-thin films with strong chemical bonding on a surface that cannot be easily achieved by other conventional methods.

Abstract: In a power semiconductor component a ceramic substrate (SUB) and a metallic baseplate (BP) are connected, in order, via a connecting layer (2), a buffer layer (DP) made of a material having a low yield point and high thermal conductivity as well as a further connecting layer (3). The mechanical connections between the ceramic substrate and the baseplate have a high shear strength. Premature material fatigue and cracking on account of the different thermal expansion of the ceramic substrate and the baseplate are avoided by means of plastic deformation of the buffer layer. Connecting layers are, for example, sintered silver powder layers such as are advantageously used in the low-temperature connection technique for power semiconductor components.