Abstract: A molded semiconductor package includes: a mold compound; a metal substrate partly embedded in the mold compound; at least one first metal lead partly embedded in the mold compound; an inlay embedded in the mold compound, the inlay comprising a semiconductor die embedded in an electrically insulating body, a first metal structure attached to a first side of the semiconductor die, and a second metal structure attached to a second side of the semiconductor die; and a metal clip at least partly embedded in the mold compound and connecting the second metal structure to the at least one first metal lead. The semiconductor die has a maximum junction temperature higher than a glass transition temperature of the mold compound, the electrically insulating body has a glass transition temperature at or above the maximum junction temperature of the semiconductor die, and the metal substrate is attached to the first metal structure.

Abstract: A method for forming spacers of a gate of a transistor is provided, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions, and basal portions covering the active layer; anisotropically modifying the basal portions by implantation of hydrogen-based ions in a direction parallel to the lateral sides of the gate, forming modified basal portions; annealing desorbing the hydrogen from the active layer and transforming the modified basal portions into second modified basal portions; and removing the modified basal portions by selective etching of the modified dielectric material with respect to the non-modified dielectric material and with respect to the semiconductive material, so as to form the spacers on the lateral sides of the gate.

Abstract: The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate having an active area disposed over or in the semiconductor substrate, and a first isolation member extending into the semiconductor substrate and disposed adjacent to the active area; disposing an energy-decomposable mask over the semiconductor substrate and the first isolation member; irradiating a portion of the energy-decomposable mask with an electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated with the electromagnetic radiation to form a patterned energy-decomposable mask; removing a portion of the semiconductor substrate exposed through the patterned energy-decomposable mask to form a trench; removing the patterned energy-decomposable mask; and forming a second isolation member within the trench.

Abstract: A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer. A gate finger and first and second source/drain contacts are provided on the semiconductor layer structure. A first source/drain region is provided in the semiconductor layer structure that includes a first implanted region that is underneath the first source/drain contact and a first auxiliary implanted region. A depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region. The first source/drain region extends inwardly a first distance from a lower edge of an inner sidewall of the first source/drain contact, and extends outwardly a second smaller distance from a lower edge of an outer sidewall of the first source/drain contact.

Abstract: On-chip peltier cooling devices and manufacturing methods thereof are provided. The device comprises: a first type well, a polysilicon gate and dummy gates, first type doped regions, a second type doped region, a first and second via. The dummy gate is formed as a two-segment structure with an interval, and there is no gate oxide layer between portions of the dummy gate which are far away from the interval and the semiconductor substrate. The first type doped region at least overlaps with an orthographic projection region of the first segment of the dummy gate on the semiconductor substrate. The second type doped region at least overlaps with orthographic projection regions of the polysilicon gate and the second segment of the dummy gate on the semiconductor substrate. In this application, the heat flows from inside of the device to its surface, to realize heat dissipation and cooling.