Abstract: This multiplexer and demultiplexer features two transmission lines, one for conveying the data and a second for timing. The timing line controls both the shifting of data in the demultiplexer and the signaling for the beginning and end of data words. Synchronization of the bit shifting clock with the word shifting signal is accomplished by means of phase lock loop circuitry incorporated into the demultiplexer. The disclosed circuit uses low power CMOS design, directly interfaces with contact closure commands, and directly drives relay or lamp type loads. The demultiplexer contains a power-up delay circuit to avoid start-up ambiguities and false data transmission.

Abstract: The monitoring peripheral equipment is intended to inform the exchange's central unit about the state and nature of the subscriber's receiver and it comprises: a circuit sensing the positions of the relays of the line equipment, a memory unit, an internal logic with a scanner thereof, a liaison circuit logic and a line equipment monitoring device, whereby the lifting of a subscriber's receiver is detected, the information is sent to the internal logic as regards the location, state and processing to be performed, said central unit calls back said liaison circuit logic and the internal logic sets the subscriber's telephone in the connected position.