Patents Examined by Duc Doan
  • Patent number: 10394462
    Abstract: A multi-tenant database may maintain a plurality of datasets on a memory device that is subject to degraded operation caused by a subset of possible state transitions within the device's memory cells. A storage engine may identify entropy characteristics of datasets, independently of other datasets hosted on the memory, and use the entropy to construct a symbol table that maps from data within the dataset to symbols that may be stored on the memory device with a minimized number of state transitions.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 27, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Adam Douglas Morley
  • Patent number: 10154113
    Abstract: A computer system according to one preferred embodiment of the present invention has a server and a storage subsystem, wherein the server is configured to enable data write to a cache area of the storage subsystem. Further, the server manages the usages of the cache area. When storing data from the server to the cache area, the server determines whether a data-writable area exists in the cache area or not. If there is a writable area, data is stored in the writable area.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: December 11, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuro Honmura, Yoshifumi Fujikawa, Keisuke Hatasaki, Mitsuhiro Okada, Akifumi Suzuki
  • Patent number: 10146632
    Abstract: An information handling system and method allows implementation of fault-tolerant storage subsystems using multiple storage controllers not themselves originally designed to support the redundancy of such fault-tolerant storage subsystems. In accordance with one embodiment, uncommitted data is efficiently and rapidly replicated across multiple commodity storage controllers, enabling faster and less expensive fault-tolerant storage subsystems. A redundant storage controller system using non-redundant storage controllers can improve the efficiency of data replication while providing failure protection against controller failure. A redundant storage controller system using non-redundant storage controllers and shared memory commonly accessible to the storage controllers can be enhanced to replicate data within host memory regions to protect against non-volatile memory failure.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: December 4, 2018
    Assignee: Dell Products, LP
    Inventors: Chandrashekar Nelogal, James P. Giannoules
  • Patent number: 10146691
    Abstract: One embodiment provides for a memory system comprising a cache memory and a cache control circuit to receive a request to perform a partial cache line write to a first cache line of the cache memory, merge the request to perform the partial cache line write with a pending request to write to the first cache line, and process a merged request as a full cache line write.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Hashem Hashemi, Saurabh Sharma, Altug Koker
  • Patent number: 10120701
    Abstract: Mechanisms for moving data between different operating systems in a dual OS computing device are discussed. More particularly, embodiments of the present invention utilize the clipboard facilities supported by the operating systems, along with firmware and helper software in each OS, to move data back and forth when switching between an active and inactive operating system. The clipboard contents are preserved in non-volatile storage that is not lost across the sleep-state transitions used to switch operating systems. Helper software analyzes the clipboard contents being copied and converts them into a format recognized by the current operating system and its applications.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: November 6, 2018
    Assignee: Insyde Software Corp.
    Inventor: Timothy Andrew Lewis
  • Patent number: 10095543
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 9, 2018
    Assignee: Mellanox Technologies Ltd.
    Inventors: Patrick Robert Griffin, Mathew Hostetter, Anant Agarwal, Chyi-Chang Miao
  • Patent number: 10089494
    Abstract: A network device is provided. The network device includes a processor and a memory with code thereupon. The code when executed by the processor causes the processor to provide object files referenced in the code, randomize an order of linking the object files in the code at a link time, and create a plurality of unique static images of a binary file based upon the randomized order.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 2, 2018
    Assignee: LGS Innovations LLC
    Inventors: David Lau, Gerald R. Thompson, Gregory St.Louis, Steve Jacks
  • Patent number: 10067885
    Abstract: In one embodiment, a computer-implemented method includes inserting a set of accessed objects into a cache, where the set of accessed objects varies in size. An object includes a set of object components, and responsive to receiving a request to access the object, it is determined that the object does not fit into the cache given the set of accessed objects and a total size of the cache. A heuristic algorithm is applied, by a computer processor, to identify in the set of object components one or more object components for insertion into the cache. The heuristic algorithm considers at least a priority of the object compared to priorities of one or more objects in the set of accessed objects. The one or more object components are inserted into the cache.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Avrilia Floratou, Uday B. Kale, Nimrod Megiddo, Fatma Ozcan, Navneet S. Potti
  • Patent number: 10067718
    Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 4, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glennis Eliagh Covington, Kevin M. Brandl, Nienchi Hu, Shannon T. Kesner
  • Patent number: 10061521
    Abstract: An operation method of a storage device, which is connected to a host through an interface sharing a memory buffer of the host, includes receiving an access command from the host, anticipating data that is expected to be requested by the host with reference to the access command, reading out the anticipated data from a nonvolatile memory device and loading the read data to a first area of the memory buffer, and in a case of being requested to load the anticipated data into a second area of the memory buffer by the host, moving the anticipated data from the first area to the second area.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Sik Yun, Sil Wan Chang, Jaesub Kim, Sangyoon Oh
  • Patent number: 10055137
    Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 21, 2018
    Assignee: INTEL CORPORATION
    Inventors: Aliasgar S. Madraswala, Yogesh B. Wakchaure, David B. Carlton, Xin Guo, Ryan J. Norton
  • Patent number: 10042571
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining a region of the memory for which to store information, inserting the information into the region of the memory, and applying one or more characteristics to the region of the memory via an instruction set architecture (ISA) operation, the one or more characteristics comprising an immutable characteristic to prevent modification of the information in the region of the memory.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 7, 2018
    Assignee: INTEL CORPORATION
    Inventors: Kirk D. Brannock, Barry E. Huntley
  • Patent number: 10025792
    Abstract: According to one embodiment, a method includes presenting a medium to more than one user as being exclusively occupied by whichever user attempts to access at least one file from the medium, writing a first file managed by a first user to a data partition of the medium, and storing a first user identifier (ID) that identifies the first user as metadata to an index partition of the medium in response to writing the first file managed by the first user. In another embodiment, a method includes reading metadata from an index partition of a medium from a first user of a plurality of users, extracting first file attribute information associated with a first user ID that indicates a first user from the metadata, and reading a first file based on the first file attribute information associated with the first user ID from a data partition of the medium.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ashida, Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Terue Watanabe
  • Patent number: 10019456
    Abstract: To identify objects shared by entities and to, in turn, identify free space in nonvolatile storage, a computer system uses a probabilistic data structure which tests whether an element is a member of a set. Such probabilistic data structures are created for entities in the storage system that share objects. The probabilistic data structure for an entity represents the objects that are used by that entity. When an entity is deleted, each object used by that entity is compared to the probabilistic data structures of other entities to determine if there is a likelihood that the object is used by one or more of the other entities. If the likelihood determined for an object is above an acceptable threshold, then the object is not deleted. If the likelihood determined for an object is below the set threshold, then the object can be deleted and the corresponding storage locations can be marked as free.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 10, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Marcus Markiewicz, Nicolas Borden
  • Patent number: 10019180
    Abstract: A snapshot analysis system analyzes a plurality of data snapshots taken in connection with data stored on a block device allocated by a data storage system. The snapshot analysis system may include an ingestor capable of initially detecting new snapshots and adding a root node for the snapshots. The system may include a block device analyzer that analyzes each snapshot to determine its contents, the relationship within data structures extant within the snapshot, and the snapshot's relationship to other snapshots and/or that of other block devices. The system may also include a clustering analyzer capable of determining whether snapshots are associated with multipart block devices, such as LVM or MD RAID devices. The system may further include a block device emulator that exposes data associated with a given snapshot as an addressable block device without necessitating retrieval or exposure of the full block device to which the snapshot is associated.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 10, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Mahmood Miah, Matthew James Eddey, John Sandeep Yuhan
  • Patent number: 10007462
    Abstract: A method for data migration in solid state memory. The method includes making a first determination that a write limit of a first memory region of the solid state memory has been reached, and based on the first determination: allocating a second memory region in the solid state memory. The method further includes, based on making the first determination: migrating a first data fragment from a first memory location in the first memory region to a corresponding second memory location in the second memory region, updating a migration progress index to include the second memory location, directing future read and write requests that target memory locations included in the migration progress index to the second memory region, and directing future read and write requests that target memory locations not included in the migration progress index to the first memory region.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 26, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Richard H. Van Gaasbeck, Michael W. Shapiro
  • Patent number: 10001949
    Abstract: Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 19, 2018
    Assignee: INTEL CORPORATION
    Inventors: Irina Calciu, Justin E. Gottschlich, Tatiana Shpeisman
  • Patent number: 10001939
    Abstract: Example embodiments of the present invention relate to a method, a system, and a computer program product for managing a plurality of storage providers to allocate a second storage provider as an active storage provider. The method includes monitoring respective health states of a plurality of storage providers in a storage infrastructure and determining an unhealthy health state of a first storage provider, operating as an active storage provider, among the plurality of storage providers. The method also includes managing the plurality of storage providers to allocate a second storage provider, operating as a standby storage provider, among the plurality of storage providers as the active storage provider.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 19, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Katakam Gangadhar, Stalin Saravanakumar Thangapalam, Selvamanickam Anbalagan, Michael G. Hegerich, Anil Arun Degwekar, Anoop Ninan
  • Patent number: 9996278
    Abstract: During normal power operation, an erased free block is prepared in nonvolatile memory so that at least one erased free block is continuously available as a standby block. If a power failure occurs, volatile data and its address conversion information are written into the standby block in the nonvolatile memory.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: June 12, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Tatsuya Zettsu
  • Patent number: 9996478
    Abstract: A system and method for efficiently performing data allocation in a cache memory are described. A lookup is performed in a cache responsive to detecting an access request. If the targeted data is found in the cache and the targeted data is of a no allocate data type indicating the targeted data is not expected to be reused, then the targeted data is read from the cache without updating cache replacement policy information for the targeted data responsive to the access. If the lookup results in a miss, the targeted data is prevented from being allocated in the cache.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 12, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mark Fowler