Patents Examined by Due Ho
  • Patent number: 6345050
    Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: February 5, 2002
    Assignee: PMC-Sierra, Inc.
    Inventors: Brian D. Alleyne, Raghavan Menon, Steve Sprouse