Patents Examined by Dung A Le
  • Patent number: 10937848
    Abstract: An organic light emitting diode (OLED) display includes: a first electrode around a center point of a virtual tetragon, e.g., a virtual square; second electrodes around a first vertex and a second vertex diagonal to the first vertex of the virtual square, the second electrodes being separated from each other and with the center point of the virtual square interposed therebetween; third electrodes around a third vertex and a fourth vertex of the virtual square, the third electrodes being separated from each other and with the center point of the virtual square interposed therebetween; a pixel defining layer partially on the first electrode, the second electrodes, and the third electrodes, and partially exposing the first electrode, the second electrodes, and the third electrodes; and four spacers disposed as islands on the pixel defining layer and corresponding to four sides of the virtual square.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ok-Kyung Park, Su Yeon Yun
  • Patent number: 10930766
    Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Sanaz K. Gardner
  • Patent number: 10930782
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Wu, Chih-Chieh Yeh, Yee-Chia Yeo
  • Patent number: 10930876
    Abstract: Each of a plurality of the light-emitting units (140) includes a first electrode (110), an organic layer (120), and a second electrode (130). The first electrode (110) is light-transmitting, and the second electrode (130) is light-reflective. The organic layer (120) is located between the first electrode (110) and the second electrode (130). The light-transmitting regions (104 and 106) are located between the plurality of light-emitting units (140). A sealing member (170) covers the plurality of light-emitting units (140) and the light-transmitting regions (104 and 106). The sealing member (170) is fixed directly or through an insulating layer (174) to at least one of a structure (for example, the second electrode 130) formed on a substrate (100), and the substrate (100). In addition, a haze value of the light-emitting device (10) is equal to or less than 2.0%, preferably equal to or less than 1.4%.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 23, 2021
    Assignee: PIONEER CORPORATION
    Inventors: Takeru Okada, Ayako Yoshida
  • Patent number: 10930505
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10926999
    Abstract: In accordance with an embodiment, a microelectromechanical transducer includes a displaceable membrane having an undulated section comprising at least one undulation trough and at least one undulation peak and a plurality of piezoelectric unit cells. At least one piezoelectric unit cell is provided in each case in at least one undulation trough and at least one undulation peak, where each piezoelectric unit cell has a piezoelectric layer and at least one electrode in electrical contact with the piezoelectric layer. The membrane may be formed as a planar component having a substantially larger extent in a first and a second spatial direction, which are orthogonal to one another, than in a third spatial direction, which is orthogonal to the first and the second spatial direction and defines an axial direction of the membrane.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: February 23, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Christian Bretthauer, Alfons Dehe, Alfred Sigi
  • Patent number: 10930744
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor layer, a first electrode, a second electrode, and a control electrode. The oxide semiconductor layer includes tin and tungsten. An average coordination number of oxygen atoms to tin atoms is greater than 3 but less than 4. The first electrode is electrically connected to a first end portion of the oxide semiconductor layer. The second electrode is electrically connected to a second end portion of the oxide semiconductor layer on a side opposite to the first end portion. The control electrode opposes a portion of the oxide semiconductor layer between the first end portion and the second end portion.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventor: Nobuki Kanrei
  • Patent number: 10921499
    Abstract: A display device includes a display panel including a plurality of light emitters spaced apart by a first representative distance in a first emission region and a plurality of light emitters spaced apart by a second representative distance different from the first representative distance in a second emission region that surrounds the first emission region. The display device also includes a filter coupled with the display panel for transmitting light projected by the display panel through the filter. The filter has a first filter region configured to cause a first distribution of light emitted from a first light emitter in the first emission region and a second distribution of light emitted from a second light emitter in the first emission region so that the first distribution at least partially overlaps with the second distribution.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: February 16, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Andrew John Ouderkirk, James Ronald Bonar, Jasmine Soria Sears
  • Patent number: 10923626
    Abstract: LEDs and methods of forming LEDs with various structural configurations to mitigate non-radiative recombination at the LED sidewalls are described. The various configurations described include combinations of LED sidewall surface diffusion with pillar structure, modulated doping profiles to form an n-p superlattice along the LED sidewalls, and selectively etched cladding layers to create entry points for shallow doping or regrowth layers.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: February 16, 2021
    Inventors: David P. Bour, Dmitry S. Sizov, Daniel A. Haeger, Xiaobin Xin
  • Patent number: 10923476
    Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
  • Patent number: 10916695
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a variable resistance element that exhibits different resistance states for storing data; and a lower contact plug coupled to the variable resistance element and disposed under the variable resistance element, and wherein a width of the lower contact plug increases from a top surface of the lower contact plug to a bottom surface of the lower contact plug.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Jin-Won Park
  • Patent number: 10916663
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Patent number: 10916494
    Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Abdolreza Langari, Yuan Li, Shrestha Ganguly, Terence Cheung, Ching-Liou Huang, Hui Wang
  • Patent number: 10910437
    Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ombretta Donghi, Marcello Ravasio, Samuele Sciarrillo, Roberto Somaschini
  • Patent number: 10910353
    Abstract: A white light source includes an arrangement of light-emitting diodes, wherein the light-emitting diodes are subdivided into first light-emitting diodes and second light-emitting diodes, and a conversion element configured to absorb light emitted by the light-emitting diodes and generate converted light with a longer wavelength than the emitted light, wherein the conversion element includes a first luminescent conversion material in a first matrix material, the first matrix material with the first luminescent conversion material is arranged two-dimensionally in a continuous layer above the first and second light-emitting diodes, the conversion element includes a second luminescent conversion material in a second matrix material, and the second matrix material with the second luminescent conversion material is arranged only above the second light-emitting diodes.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 2, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Burger, Désirée Queren
  • Patent number: 10903248
    Abstract: A thin film transistor array substrate includes a substrate, at least one thin film transistor, a capacitor, an interlayer insulating layer, and a node connection line. The at least one thin film transistor is on the substrate. The capacitor is on the substrate and includes: a bottom electrode on the substrate; a top electrode overlapping the bottom electrode, the top electrode including an opening having a single closed curve shape; and a dielectric layer between the bottom electrode and the top electrode. The interlayer insulating layer covers the capacitor. The node connection line is on the interlayer insulating layer and electrically connects the capacitor to the at least one thin film transistor. An overlapping area of the bottom electrode and the top electrode is divided by the opening into two separate areas.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 26, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hansung Bae, Wonkyu Kwak
  • Patent number: 10903422
    Abstract: A method for fabricating a semiconductor device including a vertically oriented memory structure includes forming at least one pillar including phase-change memory (PCM) material on at least one electrode, forming a plurality of spacers on the electrode and along sidewalls of the pillar, and forming, by processing the plurality of spacers and the pillar, a modified pillar having a vertically oriented dumbbell shape associated with a vertically oriented PCM memory structure.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10892219
    Abstract: Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli
  • Patent number: 10892355
    Abstract: Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 12, 2021
    Assignee: HRL Laboratories, LLC
    Inventor: Biqin Huang
  • Patent number: 10886370
    Abstract: A silicon carbide body includes a drift structure having a first conductivity type, a body region, and a shielding region. The body and shielding regions, of a second conductivity type, are located between the drift structure and a first surface of the silicon carbide body. First and second trench gate stripes extend into the silicon carbide body. The body region is in contact with a first sidewall of the first trench gate stripe. The shielding region is in contact with a second sidewall of the second trench gate stripe. The second sidewall has a first length in a lateral first direction parallel to the first surface. A supplementary region of the first conductivity type contacts one or more interface areas of the second sidewall. The one or more interface areas have a combined second length along the first direction, the second length being at most 40% of the first length.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 5, 2021
    Assignee: Infineon Technologies AG
    Inventors: Florian Grasse, Axel Sascha Baier, Wolfgang Bergner, Barbara Englert, Christian Strenger