Patents Examined by Dung A Le
  • Patent number: 10566262
    Abstract: Exemplary embodiments are disclosed of thermal interface materials with wear-resisting layers and/or suitable for use between sliding components. Also disclosed are devices including thermal interface materials and methods of using thermal interface materials.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 18, 2020
    Assignee: Laird Technologies, Inc.
    Inventors: Jingqi Zhao, Licai Jiao
  • Patent number: 10566247
    Abstract: Semiconductor devices and methods are provided to fabricate field effect transistor (FET) devices having local wiring between the stacked devices. For example, a semiconductor device includes a first FET device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer. The semiconductor device further includes a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration. The semiconductor device further includes one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10560771
    Abstract: In accordance with an embodiment, microelectromechanical microphone includes a holder and a sound detection unit carried on the holder. The sound detection unit includes a planar first membrane, a planar second membrane arranged at a distance from the first membrane, a low-pressure chamber formed between the first membrane and the second membrane, a reduced gas pressure relative to normal pressure being present in the low-pressure chamber, a reference electrode arranged at least in sections in the low-pressure chamber, where the first and second membranes are displaceable relative to the reference electrode by sound waves to be detected, the reference electrode includes a planar base section and a stiffening structure provided on the base section, and the stiffening structure is provided on a side of the base section that faces the first membrane or/and on a side of the base section that faces the second membrane.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Alfons Dehe, Gerhard Metzger-Brueckl, Johann Strasser, Arnaud Walther, Andreas Wiesbauer
  • Patent number: 10553758
    Abstract: The semiconductor layer has a first surface, a second surface provided on opposite side from the first surface, and a third surface provided on the opposite side from the first surface with a step difference with respect to the second surface. The semiconductor layer includes a light emitting layer between the first surface and the third surface. The first electrode is in contact with the second surface. The second electrode is provided in a plane of the third surface. The second electrode includes a contact part in contact with the third surface and an end part not in contact with the third surface. The second electrode contains silver. The insulating film is provided between the end part of the second electrode and the third surface. A semiconductor light emitting device having a high light extraction efficiency is provided.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 4, 2020
    Assignee: ALPAD Corporation
    Inventors: Hideyuki Tomizawa, Akihiro Kojima, Miyoko Shimada, Yosuke Akimoto, Hideto Furuyama, Yoshiaki Sugizaki
  • Patent number: 10553499
    Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 4, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Franck Julien, Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret
  • Patent number: 10546800
    Abstract: A semiconductor module includes: a semiconductor device having an upper surface electrode; a conductor plate joined to the upper surface electrode via a bonding member; and a wire bonded to the conductor plate, wherein the wire is a metal thread or a ribbon bond, and the bonding member is a porous sintered metal material impregnated with resin.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasunari Hino, Yuji Sato
  • Patent number: 10546835
    Abstract: Embodiments of the invention include a microelectronic device that includes a transceiver coupled to a first substrate and a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. An interposer substrate can provide a spacing between the first and second substrates.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Georgios C. Dogiamis, Telesphor Kamgaing
  • Patent number: 10541246
    Abstract: 3-d flash memory cells and methods of manufacture are described. The devices and methods recess a compound floating gate in between the silicon oxide slabs which reduces the quantum probability of electron tunneling between vertically adjacent storage cells. The devices and methods further include a high work function nanocrystalline metal in the compound floating gate. A polysilicon buffer layer forms a portion of the compound floating gate. The polysilicon buffer layer allows the high work function nanocrystalline metal to be selectively deposited. The polysilicon buffer layer further protects the high work function nanocrystalline metal from oxidation with the gate oxide subsequently formed on the other side.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 21, 2020
    Assignee: Applied Materials, Inc.
    Inventor: Vinod R. Purayath
  • Patent number: 10535568
    Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Han Tsao, Chii-Ming Wu, Cheng-Yuan Tsai, Yi-Huan Chen
  • Patent number: 10535744
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: January 14, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Toshiya Yonehara, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Patent number: 10529735
    Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
  • Patent number: 10529845
    Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ashita Mirchandani, Thomas Feil, Maximilian Roesch, Britta Wutte
  • Patent number: 10529654
    Abstract: A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuh-Harng Chien, Chih-Chien Ho, Steven Su
  • Patent number: 10522364
    Abstract: A method including forming hard mask patterns on a substrate; forming etch stop patterns surrounding the hard mask patterns; forming spacer patterns covering sidewalls of the etch stop patterns; removing the etch stop patterns; etching the substrate to form active and dummy fins; forming a block mask pattern layer surrounding the active and dummy fins and forming mask etch patterns on a top surface of the block mask pattern layer; etching the block mask pattern layer to form block mask patterns surrounding the active fins; etching the dummy fins; removing the block mask patterns surrounding the active fins; and depositing a device isolation film on the substrate such that the device isolation film is not in contact with the upper portions of the active fins, wherein a spacing distance between the active fin and the dummy fin is greater than an active fin spacing distance between the active fins.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Min Kim, Dong Won Kim
  • Patent number: 10522718
    Abstract: A light-emitting semiconductor chip comprises: a radiation-transmissive substrate, an epitaxially grown semiconductor layer sequence on a main surface of the substrate, a first contact and a second contact on a contact surface of the semiconductor layer sequence facing away from the substrate for electrical and mechanical contacting of the semiconductor chip, a transparent, electrically conductive layer which is arranged on the contact side and is electrically connected to the first contact.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 31, 2019
    Assignee: OSRAM OPTO SEMICONDCUTORS GMBH
    Inventor: Ivar Tångring
  • Patent number: 10515793
    Abstract: A device includes a fin structure, a dielectric layer, a gate a spacer, and an epitaxy structure. The dielectric layer is over the fin structure. The gate is over the dielectric layer. The spacer is on a sidewall of the gate. The spacer has a thickness along a direction parallel to a longitudinal axis of the fin structure, and a distance along the direction from an outer sidewall of the spacer to an end surface of the fin structure is greater than the thickness of the spacer. The epitaxy structure is in contact with the fin structure.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10503034
    Abstract: The present invention provides a manufacturing method of a TFT substrate and structure. The manufacturing method of the TFT substrate deposit a black photoresist on the second passivation layer (PV2) and patterning to form a main integrated photoresist spacer (61), a sub-photoresist spacer (62) and a black matrix (63), then depositing a transparent conductive film on the integrated main photoresist spacer, the sub-photoresist spacer and the black matrix and patterning to form a pixel electrode (71) and a common electrode (72).
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 10, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yanxi Ye
  • Patent number: 10504852
    Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Patent number: 10497846
    Abstract: A light emitting device package according to an embodiment includes: a body including first and second openings passing through an upper surface of the body and a lower surface of the body; a light emitting device disposed on the body and including first and second bonding parts; and first and second conductive layers disposed under the body and electrically connected to the first and second bonding parts, respectively, wherein each of the first and second bonding parts includes a protrusion portion protruding and extending in a downwards direction within the first and second openings, respectively.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 3, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Tae Sung Lee, Chang Man Lim, June O Song
  • Patent number: 10497736
    Abstract: A backside illuminated image sensor includes pixel regions disposed in a substrate, an anti-reflective layer disposed on a backside surface of the substrate, a light-blocking pattern disposed on the anti-reflective layer and having openings corresponding to the pixel regions, a color filter layer disposed on the light-blocking pattern, and a micro lens array disposed on the color filter layer, wherein the light-blocking pattern has a width decreasing toward the backside surface of the substrate.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 3, 2019
    Assignee: DB HITEK CO., LTD.
    Inventor: Chang Hun Han