Abstract: A new Power DFN and Power QFN package architecture that accommodates Bump-chip die and other components in cavities on the bottom-side of the matrix leadframe, and the technique is also applicable to laminated substrate packages like the BGA and LGA. The package is especially suited for high speed power compound semiconductor devices like GaN and SiC. The package enables single and multiple power switch configurations, and well controlled paralleling of high speed power die switches. It enables co-packaging of associated components like cascoded switchs, gate drivers, isolators and protection devices, which must be tightly coupled at high switching speeds. The architecture accommodates components on the top-side of the leadframe as well allowing for multi-chip functions with extremely low interconnect inductance and resistance, and higher circuit and power densities.

Abstract: According to an embodiment, a semiconductor light emitting device includes a stacked body, first and second electrodes, first and second interconnections, first and second pillars and a first insulating layer. The stacked body includes first and second semiconductor layers and a light emitting layer. The first and second electrodes are connected to the first and second semiconductor layers respectively. The first and second interconnections are connected to the first and second electrode respectively. The first and second pillars are connected to the first and second interconnections respectively. The first insulating layer is provided on the interconnections and the pillars. The first and second pillars have first and second monitor pads exposed in a surface of the first insulating layer. The first and second interconnections have first and second bonding pads exposed in a side face connected with the surface of the first insulating layer.

Abstract: Provided are semiconductor devices that may include a substrate provided with a transistor, an insulating layer disposed on the substrate, the insulating layer including a contact hole exposing a portion of the transistor, a spacer disposed on an inner sidewall of the contact hole, and a contact plug disposed in the contact hole. Here, a space defined by the spacer may increase in width from a bottom side thereof to a top side thereof.

Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized.

Abstract: A method for fabricating transistors such as high electron mobility transistors, each transistor comprising a plurality of epitaxial layers on a common substrate, method comprising: (a) forming a plurality of source contacts on a first surface of the plurality of epitaxial layers; (b) forming at least one drain contact on the first surface; (c) forming at least one gate contact on the first surface; (d) forming at least one insulating layer over and between the gate contacts, source contacts and the drain contacts; (e) forming a conductive layer over at least a part of the at least one insulating layer for connecting the source contacts; and (f) forming at least one heat sink layer over the conductive layer.

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.

Abstract: A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

Abstract: An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the integrated circuit system; and transferring a stress from the stress memorization layer to the gate and the source/drain region.

Abstract: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

Abstract: A sensor system having a substrate and a housing and a method for manufacturing a sensor system are provided, the housing essentially completely enclosing the substrate in a first substrate region, the housing in a second substrate region being provided at least partially open via an opening, the second substrate region in the region of the opening being provided so as to project from the housing, the housing being manufactured using an injection molding compound and being molded in such a way that the injection molding compound has only one flow front.

Abstract: A method of joining two silicon members and the bonded assembly in which the members are assembled to place them into alignment across a seam. Silicon derived from silicon powder is plasma sprayed across the seam and forms a silicon coating that bonds to the silicon members on each side of the seam to thereby bond together the members. The plasma sprayed silicon may seal an underlying bond of spin-on glass or may act as the primary bond, in which case through mortise holes are preferred so that two layers of silicon are plasma sprayed on opposing ends of the mortise holes. A silicon wafer tower or boat may be the final product. The method may be used to form a ring or a tube from segments or staves arranged in a circle. Plasma spraying silicon may repair a crack or chip formed in a silicon member.

Abstract: A structure of a tag integrated circuit flexible board includes a base material, one surface thereof having an adhesive layer; and a plurality of integrated circuit flexible boards that are arranged adjacent to one another and adhered on the adhesive layer of the base material. The integrated circuit flexible board includes an insulating heat-conductive material, and a conductive circuit layer provided on a surface of the insulating heat-conductive material and formed of a plurality of sections of circuits.

Abstract: Embodiments relate to a method for fabricating a semiconductor device. In embodiments, the method may include forming a gate dielectric layer on an active region of a semiconductor substrate defined by an isolation region to form a gate conductive layer pattern, etching the isolation region of the semiconductor substrate where the gate conductive layer pattern is formed, to form an isolation trench, forming a polyoxide layer on the gate conductive layer pattern and a sidewall oxide layer in the trench by carrying out an oxidation process, forming a spacer nitride layer on the polyoxide layer and a liner nitride layer on the sidewall oxide layer by carrying out a nitride layer forming process, and then forming a dielectric layer on an entire surface of the resultant structure to fill the trench.

Abstract: The present invention aims at providing a method for dividing a substrate that is capable of dividing each substrate into chips in the same square-like form without causing chip breaking and capable of forming all cleaved facets flat. In the method for dividing a substrate of the present invention, an electron beam 1 with the intensity that causes a dislocation inside the substrate is irradiated to a substrate surface 2 to generate a crack starting from such dislocation, and a cleaved facet 5 is formed to divide the substrate.

Abstract: A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. Then a first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. Then conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. Then the semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.

Abstract: A structure comprises a deep sub-collector buried in a first epitaxial layer and a near sub-collector buried in a second epitaxial layer. The structure further comprises a deep trench isolation structure isolating a region which is substantially above the deep sub-collector, a reach-through structure in contact with the near sub-collector, and a reach-through structure in contact with the deep sub-collector to provide a low-resistance shunt, which prevents COMS latch-up of a device. The method includes forming a merged triple well double epitaxy/double sub-collector structure.

Abstract: Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate oxide, a silicon-containing barrier layer and a gate electrode. The gate oxide is formed over the substrate. The silicon-containing barrier layer is formed over the gate oxide by causing silicon atoms of a precursor layer react with a reactive agent. The gate electrode is formed over the silicon-containing barrier layer. Other embodiments utilizing a barrier layer are disclosed.

Abstract: The present invention proposes a novel method to fabricate a Bipolar Junction Transistor device. The steps of the present invention include forming a shallow trench isolation structure in a substrate. An oxide layer is formed on the substrate. Subsequently, a polysilicon layer is next formed on the oxide layer, and the polysilicon layer has first type ion. Successively, a polysilicon layer is patterned on the oxide layer. The next step is to perform a second type ion implantation, thereby forming a collector region in the substrate and below the emitter window. The oxide layer is removed inside the emitter window. An expitaxy base is then formed on the polysilicon layer and substrate, thereby forming base region on the collector region, wherein the expitaxy base has the first type ion. After the expitaxy base is formed, a dielectric layer is formed over the expitaxy base. Next, the dielectric layer is etched to form inner spacer on sidewalls of the expitaxy base inside the emitter window.