Abstract: A method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) is provided. Specifically, the present invention provides a method for applying an oxide layer to a silicon carbide substrate so that the oxide-substrate interface of the resulting SiC MOSFET is improved. The method includes forming the oxide layer in the presence of metallic impurities.

Abstract: This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front and back surfaces of a semiconductor material wafer. The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface of the semiconductor wafer prior to starting the manufacturing process for the electronic devices, and also can be before the step of cleaning the front surface of the wafer.

Abstract: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Abstract: A process for forming a nitrogen enriched ultra thin gate oxide is described. The nitrogen enrichment increases the dielectric constant of the gate oxide thereby decreasing it's effective oxide thickness. This in turn enhances the performance of MOSFET devices formed thereon. The nitrogen enrichment is accomplished by first enriching the surface of a silicon wafer with nitrogen by implanting nitrogen atoms into the silicon through a sacrificial screen oxide. After fixing the nitrogen by annealing, a nitrogen enriched gate oxide is thermally grown. Additional nitrogen is then infused into the gate oxide by remote plasma nitridation. This two step nitrogen enrichment process increases the dielectric constant of the gate oxide by a significant amount, approaching that of silicon nitride which not only decreases it's effective thickness with respect to gate capacitance, but also lowers device leakage by suppressing hot carrier injection over device drain regions.

Abstract: To control the positional relation between semiconductor regions formed on an epitaxial layer after the epitaxial layer is formed with high accuracy in a method for manufacturing semiconductor devices in which a plurality of semiconductor regions are formed selectively on the epitaxial layer on the semiconductor surface having a semiconductor region formed selectively on the semiconductor surface, a first wafer alignment mark is formed on the semiconductor substrate surface to be served as the under layer of an epitaxial layer which will be formed subsequently, and the wafer alignment mark is used as an index for wafer alignment for forming selectively a semiconductor region, and a second wafer alignment mark is formed on the surface of the epitaxial layer after the epitaxial layer is formed, and the second wafer alignment mark is used as an index for wafer alignment for forming respective semiconductor regions on the epitaxial layer.

Abstract: A semiconductor device having a double layer type anti-reflective layer, which can reduce reflectivity in a photolithography process using, for example, an exposure light source of a 193 nm wavelength region and which can suppress intermixing at the boundary between an anti-reflective layer and a photoresist layer, and a fabrication method of the semiconductor device are disclosed. The semiconductor device includes an underlying layer having a high reflectivity formed on a semiconductor substrate, a double layer type anti-reflective layer formed of a nitride layer and a layer formed using only hydrocarbon-based gas on the underlying layer, and a photoresist layer formed on the double layer type anti-reflective layer. In the double layer type anti-reflective layer, the nitride layer and the layer formed using only hydrocarbon-based gas can be sequentially stacked. Also, it is possible that the layer formed using only hydrocarbon-based gas and the nitride layer are sequentially stacked.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: A Schottky barrier semiconductor device comprises an n+-type semiconductor substrate, an n−-type semiconductor layer grown on the semiconductor substrate by epitaxial growth, and two or more adjacent p+-type semiconductor regions formed on a surface of the semiconductor layer. The device comprises a metal layer having a Schottky barrier on the surface of an active region of the semiconductor layer. The p+-type semiconductor regions are formed so that a ratio of a distance between the adjacent p+-type semiconductor regions to a distance between the bottom surface of the p+-type semiconductor region and the bottom surface of the semiconductor layer may be the ratio of 1 to 1 through 2.

Abstract: The present invention provides a method of forming a contact hole of a DRAM on a semiconductor wafer. The semiconductor wafer comprises a substrate, a conductive layer positioned in a predetermined area of the substrate and a dielectric layer positioned on the surface of the substrate and covering the conductive layer. The method comprises forming an amorphous silicon ( &agr;-Si) layer with an opening on the surface of the dielectric layer wherein the opening is positioned directly above the conductive layer and penetrates to the surface of the dielectric layer, forming a polysilicon layer uniformly on the surface of the amorphous silicon layer and performing a dry etching process to form a contact hole in the dielectric layer, the amorphous silicon layer and the polysilicon layer being used as a hard mask, the contact hole penetrating through the dielectric layer down to the surface of the conductive layer.

Abstract: A process is provided for producing a photovoltaic element which has at least one pin junction, and a buffering semiconductor layer constituted of plural sublayers between an n-type layer and an i-type layer and/or between an i-type layer and a p-type layer, through production steps of introducing a source material gas into an electric discharge space in a reaction chamber, and decomposing the source material gas by plasma discharge to form a non-monocrystalline semiconductor layer. In the process, in electric discharge generation for formation of at least one of the sublayers, the polarity of the electrode confronting the substrate for formation of a first sublayer and the polarity of the electrode confronting the substrate for formation of a second sublayer adjacent to the first sublayer is made different from each other, or the potential of one of the electrodes is set at zero volt. Thereby, diffusion of the dopant from the p-type layer or the n-type layer into the i-type layer is prevented effectively.

Abstract: A method is disclosed for forming an epitaxial layer of a semiconductor material over a metal structure disposed upon a surface of a semiconductor substrate, the metal being characterized by a negative Gibbs free energy for the formation of a compound of the metal and the semiconductor material. The method comprises the steps of: a) placing the substrate in a reactor vessel having a base pressure in the ultra high vacuum range, b) bringing the substrate to an elevated temperature, and c) flowing, over said substrate, a halogen-free precursor gas of molecules comprising the semiconductor material. Typically, the metal structure characterized by feature dimensions of less than 2.0 microns. Preferably, the metal is tungsten, the semiconductor material is silicon and the gas comprises a silane of the form SinH(2n+2), where n is a positive integer.

Abstract: A method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein the dual damascene opening exposes the conductive layer. The trench is larger than the dual damascene opening. A conformal barrier layer is formed on the dielectric layer. A conformal metal layer is formed on the barrier layer to fill the dual damascene opening and to partially fill the trench. The metal layer positioned in the trench has a thickness equal to the depth of the trench. A conformal cap layer is formed on the metal layer. A CMP process is performed to remove the cap layer, the metal layer and the barrier layer outside the trench and outside the dual damascene opening.