Abstract: Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and a drain region of the substrate are doped, with the first and second spacers correspondingly masking first and second regions of the substrate. The first and second spacers are removed after doping and the first and second regions are exposed. The exposed first and second regions are then doped. The substrate is heated after this second doping stage to simultaneously activate dopant in the source region, the drain region, the first region, and the second region. A third spacer is then formed on the first region and a fourth spacer is then formed on the second region. A suicide contact is established with at least the transistor member, the source region, or the drain region after formation of the third and fourth spacers.

Abstract: A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area is etched to form a lower gate trench having a predetermined width. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate.