Abstract: A method of handling I/O operations in a multiprocessor system which includes a plurality of host processors that are connected to a data storage system through corresponding connections, wherein the data storage system includes a lock manager and wherein the plurality of host processors communicate over the connections with the data storage system by using an interface protocol which permits only a single command to be sent during each complete transfer over the connection.

Abstract: A method implemented on a computer system for loading a module for input and for loading a module for output for an application program includes the steps of selecting the module for input, loading the module for input, selecting a module for output, and loading the module for output at a time different from the loading of the module for input.

Abstract: A computer system includes a software UART emulation and uses standard operating system protocols to minimized the chance of I/O conflicts between a serial device having a UART and a non-standard serial device which communicates through the UART emulation. A COM driver which can replace a standard COM driver in an operating environment such as provided by Microsoft WINDOWS.TM. contains the UART emulation. The COM driver can also include a software modem that is accessed through the UART emulation in the same manner as a modem having a hardware UART. The COM driver also sets the device address of the non-standard device on an ISA bus by determining the device addresses of COM port I/O slots used by UARTs, sending a predetermined pattern on the ISA bus to indicate a device address is to come, and then sending a value indicating a device address not used by the UARTs. The pattern has a length sufficient to make inadvertent generation of the pattern unlikely.

Abstract: A message control system is for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit (13) within each processing module (10) includes a data processing part (14) which is a software running on a central processing unit (11) within its own processing module, and a buffer (16, 17) which stores a transmitting message. A connection unit (13) within each processing module (10) at least includes a plurality of logical transmitting ports (21) for successively reading out the message which is expanded in the buffer (16, 17) and transmits the same as a continuous message, a plurality of logical receiving ports (22) for storing the message, a transmission system connecting means (23), and a reception system connecting means (24).

Abstract: A synchronous bus controller which provides a functional control link between one or more microprocessors and an asychronous main input/output bus is provided. The bus controller includes a state machine and data bus width determining logic enabling the bus controller to initiate and control access operations between microprocessors and accessible devices on the main input/output bus when the microprocessor and the accessed device may have different data bus widths. The bus controller includes logic circuitry to determine the number of access cycles required to complete a requested access operation and detects the last access cycle of a current access operation to terminate an access operation and provide a ready signal to the microprocessor indicating that the bus controller is ready for the next access request.