Abstract: A QLED device and manufacturing method thereof, a QLED display panel and a QLED display device are disclosed which improve the surface and internal structure of the quantum dot layer in the QLED devices. The method for manufacturing a QLED device includes forming a first electrode layer; forming a quantum dot layer on the first electrode layer; infiltrating a mixed solvent containing a bifunctional molecule into the quantum dot layer so as to improve the structure of the quantum dot layer; and forming a second electrode layer on the quantum dot layer.

Abstract: A complementary thin film transistor includes an N-type metal oxide thin film transistor and a P-type metal oxide thin film transistor. A method of manufacturing a complementary thin film transistor is also provided. The method includes forming a complementary thin film transistor including an N-type metal oxide thin film transistor and a P-type metal oxide thin film transistor. An array substrate including the complementary thin film transistor and a display device including the array substrate are further provided.

Abstract: Various embodiments of the present disclosure include a non-volatile memory semiconductor device and a device that uses the same, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present disclosure, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.

Abstract: A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film includes a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.

Abstract: An organic light emitting diode (OLED) display includes: a first electrode around a center point of a virtual tetragon, e.g., a virtual square; second electrodes around a first vertex and a second vertex diagonal to the first vertex of the virtual square, the second electrodes being separated from each other and with the center point of the virtual square interposed therebetween; third electrodes around a third vertex and a fourth vertex of the virtual square, the third electrodes being separated from each other and with the center point of the virtual square interposed therebetween; a pixel defining layer partially on the first electrode, the second electrodes, and the third electrodes, and partially exposing the first electrode, the second electrodes, and the third electrodes; and four spacers disposed as islands on the pixel defining layer and corresponding to four sides of the virtual square.

Abstract: A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface opposite to the first surface. The package is disposed over the substrate. The first conductors are disposed over the substrate. The second conductors are disposed over the substrate, wherein the first conductors and the second conductors are substantially at a same tier, and a width of the second conductor is larger than a width of the first conductor.

Abstract: A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.

Abstract: A die includes a plurality of dielectric landings and a conductive material distributed across one or more of the plurality of dielectric landings. Each one of the plurality of dielectric landings electrically separates two conductive landings associated with the one of the plurality of dielectric landings. The conductive material establishes an electrical connection between the two conductive landings associated with the one or more of the plurality of dielectric landings.

Abstract: A display device according to an embodiment of the present invention includes a base material containing resin and including a display region and a bent region, the display region including a plurality of pixels; and a resin layer disposed on one side of the base material. An exposed section where a surface of the resin layer on a side opposite to a side on which the base material is disposed is exposed is formed in at least the bent region, and the resin layer includes, in the exposed section, a first resin layer and a second resin layer whose hydrophilicity is lower than that of the first resin layer, in this order from the base material side.

Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

Abstract: A substrate for a display device and a display device including the same are disclosed. The substrate includes a first thin-film transistor including an oxide semiconductor layer, a second thin-film transistor spaced apart from the first thin-film transistor and including a polycrystalline semiconductor layer, and a storage capacitor including at least two storage electrodes. One of the at least two storage electrodes is located in the same plane and is formed of the same material as gate electrodes of the first thin-film transistor and the second thin-film transistor, and another one of the at least two storage electrodes is located in the same plane and is formed of the same material as source and drain electrodes of the first thin-film transistor and the second thin-film transistor. Accordingly, lower power consumption and a larger area of the substrate are realized.

Abstract: A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: A semiconductor device includes a device substrate having a dielectric layer and a metal wire in the dielectric layer, a first opening on the metal wire and having a bottom at a depth the same as an upper surface of the metal wire, a first insulation layer including a first color filter material on sidewalls of the first opening, a second opening disposed at opposite ends of the semiconductor device and having a bottom at a depth the same as the depth of the bottom of the first opening, and a second insulation layer including a second color filter material on sidewalls of the second opening. The first opening is for leading out the metal wire to a pad. The second opening is disposed along scribe lines. The semiconductor device simplifies the process of drawing out and isolating the pads and satisfies technical requirements of a back seal ring.

Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.

Abstract: A method of manufacturing a thin-film transistor (TFT) array substrate, including: forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer and a pixel electrode layer on a base substrate. The step of forming the source/drain electrode layer and the pixel electrode layer includes: forming a transparent conductive film and a first metallic film on the oxide semiconductor layer in sequence, to form a stack layer of the transparent conductive film and the first metallic film, in which the transparent conductive film contacts the oxide semiconductor layer; and forming source electrodes, drain electrodes and pixel electrodes by a single patterning process on the stack layer of the transparent conductive film and the first metallic film. One patterning process is saved, the production time is shortened, and the production cost is reduced.

Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.

Abstract: A method of forming source/drain contact structures that exhibit low contact resistance and improved electromigration properties is provided. After forming a first contact conductor portion composed of a metal having a high resistance to electromigration, such as, for example, tungsten, at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion composed of a highly conductive metal, such as, for example, copper or a copper alloy, is formed over the first contact conductor portion.

Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.