Abstract: A method and system for limiting access to a media storage device such as a tape drive unit. In accordance with the inventive method, a set of control parameters is generated for the device for a given application program. A tape control unit uses the parameters to process commands from the application program and thereby control access to the tape. In an illustrative application, an extent is defined on the tape and controls are defined which govern the type of access permitted within the extent. The system rejects any commands which attempt to access medium outside of the defined extent. Write and formatting commands within the extent are limited and partition changes, loads and unloads are prohibited.

Abstract: A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and peripheral device and communicating control signals to and from the peripheral device. The communication of data between the FIFO and peripheral device is effected in accordance with data communication rates which are controlled by the host and slave state machines in accordance with the commands from the command registers.

Abstract: A distributed memory computer system periodically performs memory copy among a plurality of computers by using general-purpose communication control devices and a transmission line of the CSMA/CD type. A master computer periodically generates a synchronizing packet, and transmits data for memory copy and normal data in a time slot immediately after the transmission of the synchronizing packet. Each computer other than the master computer transmits the data for memory copy and the normal data in its own time slot after the elapse of a predetermined time. The respective computers complete their transmissions within predetermined times. Since the time slots are assigned to the respective computers, the number of computers which may compete with each other on a transmission line can be restricted and each computer can be assured a periodic opportunity to transmit data.

Abstract: A method and system are provided for prioritization of the display order of received mail items. In one embodiment, the invention associates a priority sorting attribute with a first email item, sorts an inbasket list of email items by any priority sorting attribute associated with any email item in the inbasket list, said inbasket list including a listing for the first email item, and displays at least a portion of the sorted inbasket list in the sorted order. The priority sorting attribute may be associated with the first email item by either the sender or the receiver of the first email item. A priority sorting attribute may be associated by the sender with some but not all of the intended recipients of the first email item and the priority sorting attribute will then be associated with the first email item only as it is sent to those recipients with whom the priority sorting attribute has been associated.

Abstract: In a communication method for data terminal equipment, which communication method includes a function of forming a communication link comprising a plurality of B channels by having a calling terminal and a called terminal execute, via an ISDN, a plurality of call connecting procedures, and of effecting a data transmission by simultaneously using the plurality of channels of the communication link thus formed,the number of times that the call connecting procedures are executed is adjusted in accordance with conditions that prevail during a communication, and a data transmission is effected in the communication link comprising a plurality of channels, the total number of which channels corresponds to the number of times that the call connecting procedures are executed.

Abstract: In a network-connected multiprocessor computer system, good cost performance and multifunctional network control is realized. In a computer system in which a plurality of processors are connected through a network, an interrupting signal line is provided in additional transmission lines. A packet is used for inter-processor communication, and a barrier synchronization packet of a fixed length is used in barrier synchronization processing. Although a barrier synchronization packet is transferred from a sending control circuit through the same transmission line for an ordinary packet, an interrupting signal is also transferred through the interrupting signal line at the same time.

Abstract: A method and apparatus for pseudo aligned transfers to memory for processors, peripherals and memories. Alignment logic, typically coupled to a peripheral, receives a plurality of data bytes from a processor. The alignment logic uses a control header transferred with the data bytes to determine whether the data bytes require re-alignment. To effect re-alignment, the alignment logic combines, rotates, and masks the data bytes as indicated by the control header.

Abstract: A system which avoids the bandwidth inefficiencies of simply providing multiple separate and independent channels for distributing data services over television compatible networks by considering the multiple channels as one unit and managing them as one unit with an upstream bandwidth management unit. This bandwidth management unit dynamically assigns active users to unused bandwidth among multiple channels. To accomplish this, the bandwidth management unit records each request for channel bandwidth that is made, each request that is being actively fulfilled, and each request that has been completed. Thus, data service providers, such as multimedia services, can efficiently use multiple 6 megahertz television network compatible channels to distribute their data to many requesters/users at high rates of speed over a relatively inexpensive existing network.

Abstract: A distribution network has an architecture that distributes data of any format over a wide serving area. An access subnetwork receives broadband data from a plurality of information providers, preferably at least some of which are received as compressed, digital signals using asynchronous transfer mode (ATM) transport. The access subnetwork combines the broadband data from different information providers, identifies the format of the data and outputs a consolidated MPEG encoded signal to a network interface module of an end user. The network interface module receives the consolidated MPEG encoded signal and converts the consolidated MPEG encoded signal into data packets in accordance with PID values identifying the format of the data. The network interface module performs MPEG and other processing on received packet data streams, and outputs information to a corresponding digital entertainment on the basis of corresponding PID values, resulting in efficient transport of data of any format.

Abstract: An Internal I/O Facility (iIOF) having a general interface for executing I/O related applications in an Input/Ouput SubSystem (IOSS) of a computer system. IIOF applications are executed in the IOSS outside the scope of CPU applications executed under the operating system (OS) of the computer system. IIOF applications are allowed to use all facilities in the IOSS. An iIOF subchannel extension is provided for those subchannels which can execute an iIOF application. IIOF subchannel extensions contain interception control fields which determine if conventional processing for the subchannel by the IOSS is to be intercepted to execute an iIOF application. A front-end interception bit in a subchannel extension is used to initiate iIOF application execution when the subchannel is taken from the IOSS work request queue. A back-end interception bit in a subchannel extension is used to initiate iIOF application execution when the subchannel is to have status put on the IOSS interruption queue.

Abstract: A method for configuring a cache memory which configures a bus controller to select either code only, data only, or code and data for storage in the cache memory. The configuration method includes the steps of flushing the cache memory, and setting a configuration bit within a cache controller to cause the bus controller to select either code only, data only, or code and data for storage in the cache memory.

Abstract: The invention relates to a local area network interconnection system through a wide area network, certain interconnection nodes of this network being formed by a plurality of redundant pieces of interconnection equipment. According to the invention, the redundant pieces of interconnection equipment have a false physical address and a logical address in common to form a unique entity with respect to the stations of the local area network, while only a single one of the pieces of interconnection equipment of this entity performs a function of bridge/router at a given instant and the others are intended to ensure support in the case of breakdown. The redundant pieces of interconnection equipment further comprise monitoring means for monitoring their respective states by exchanges of frames on the local area network.

Abstract: A computer architecture that permits applications resident on remote "client" computers to communicate simply and efficiently with applications resident on a central server is disclosed. Client applications can effectively retrieve information from the server without detailed knowledge of server applications, the location of a requested data item or the particular hardware configuration of the host or even the client. A circuit manager module opens and maintains a communication circuit to the appropriate server application, supervising routing of messages from all client applications to that server application. The circuit manager also receives all incoming messages, routing them to the appropriate client applications. A client application can specify message destination in the form of a specific circuit (which requires substantial program awareness of communication patterns), or an identifier associated with the target application, or the type of information being requested from the server.

Abstract: An application programming interface for a digital disk recorder uses a port to link resources together to form a multimedia recorder that emulates a tape recorder while retaining the flexibility of the digital disk recorder. The port is a matrix of timelines for each resource, with each track in the port representing a media stream associated with a different one of the resources. A dynamic subsystem controls recording and playing back multimedia between the resources and a disk file system of the digital disk recorder using the port. A static subsystem maintains on the disk file system a database of movies recorded by the digital disk recorder from the resources according to the port, with each movie being a collection of media files for each resource that are independently accessible.

Abstract: In a computer network having a plurality of nodes with one or more computer systems associated with a node a method for transmitting messages to and from a DOS application resident in a memory to and from the network. The messages to and from the DOS application are handled a virtual device driver resident in the memory which is monitoring the 5C interrupt. The virtual device driver converts an outgoing CCB1 message from the DOS application to a message in a CCB3 32-bit format and an incoming 32-bit CCB3 message to a CCB1 format. The virtual device driver transmits the CCB3 message to a physical device driver resident in system memory. The physical device converts messages between the CCB3 32-bit format and a CCB3 16-bit format. The physical device driver transmits and receives 16-bit CCB3 messages to and from a logical link control protocol driver resident in the memory.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A data processing system includes one or more processing units, a memory subsystem, and one or more input/output channel controllers, wherein each of the input/output channel controllers include the capability of speculative input/output execution. The speculative I/O execution technique according to the present invention may include several options. The speculative execution in the IOCC begins after receiving a raw address even though the operation can still be remotely retried. The programmed I/O latency time is reduced significantly due to the early speculative commencement of the IOCC operation. The IOCC may have to abort the speculative operation if a remote flow control retry is received. If, however, no retry is received then significant time is saved because the speculative operation proceeds.

Abstract: A computer system which assigns a unique identifier to each component in the system. The system includes a microprocessor, a memory, and one or more components. The microprocessor and the memory are coupled by first data lines. Each component has a storage device for storing data to uniquely identify each component and second data lines, the second data lines coupled to the first data lines. The storage device includes an identification input which is coupled to a selected one of the second data lines. The storage device in each component stores data from the selected one of the second data lines during the transmission of a sequence of data from the memory on the second data lines. With the system, a unique and consistent identifier can be assigned to each component in a computer system, each time the computer system is started. A separate memory device to store an identifier for each component is unnecessary.

Abstract: An approach suited for use with an arrangement including an image processing apparatus and a server, with the server being disposed remotely of the image processing apparatus, is provided. In practice, a user accesses the remotely disposed server from the image processing apparatus by entering an appropriate personal identification number and selecting a job ticket from a directory listing the job tickets resident at the server. One of the job tickets is then selected and transmitted across the network from the server to the image processing apparatus. A job is then programmed at the image processing apparatus with the selected job ticket.

Abstract: A computer system allows for a hardware structure to participate in the transmission of P1394 packets, which are comprised of command or data blocks from linked list structures in a system memory, is disclosed. The system is able to provide dynamic appending of these command or data blocks to the link list while they are being operated upon. This provides an efficient transaction layer operation, which minimizes signalling between the link list operator or control code, and other hardware features.