Abstract: A system and methods are shown for performing a hardware performance analysis of graphics hardware and an application program. An application program generates a set of function calls. The function calls are translated to a native command set. The native command set is stored within a database. Software simulations and hardware emulations are used to compare the stored native command set data to a hardware architectural description of the graphics hardware. Data collected from the simulations are used to provide a performance model from which the performance of a graphics hardware executing commands for the application program can be determined.

Abstract: An automated simulation method for determining the enhanced generation-recombination rate due to trap-to-band tunnelling in a semiconductor device using the Dirac coulombic tunelling integral and to a simulator for carrying out the method are disclosed. The method and simulator are, for example, particularly useful in the modelling of characteristics such as leakage current in polysilicon TFTs, which leakage current can, for example, seriously degrade pixel voltage in active matrix display devices.

Abstract: In an illustrative embodiment, a desired signal processing transfer function is implemented using a generic pipelined data processor having variable latency followed by a variable latency multistage FIFO. The delay of the multistage FIFO is varied dynamically to keep the number of outstanding samples (and thus the overall latency) a constant. The present invention enables an abstract approach to the design of higher-level signal processing transfer functions while the design of the underlying low-level circuitry is driven solely by target implementation technology issues. Thus, the higher-level design of signal processing transfer functions is decoupled from the low-level (logic and physical) design. Furthermore, test bench modules and vectors for testing the transfer function can also be to be prepared independent of the specifics of the low-level circuitry associated with the target implementation technology.

Abstract: A computer system includes a printed circuit board manufactured in accordance with simulated trace impedances and topologies. The printed circuit board includes trace impedances characterizing at least three dimensions of a multi-dimensional space of the printed circuit board. The printed circuit board design includes trace impedances and topologies obtained with the use of a quasi-Monte Carlo simulation methodology.

Abstract: A method that creates a string that models a trace, the string having a collection of lumped elements, where at least one of the lumped elements has a cross capacitor. The method reduces the string to a pi model where the pi model has a cross capacitor. The method simulates the application of an applied noise voltage to the cross capacitor.

Abstract: A method of testing operation of an automated banking machine system is provided. The method may comprise storing in a data store data representative of a simulated automated banking machine, at least one condition which occurs at the machine and at least one action to be carried out responsive to the condition. The method may further comprise inputting an input representing the condition at the machine and indicating through a display, responsive to the stored data, the at least one action being carried out responsive to simulating the condition at the machine. The method may also include carrying out the at least one action responsive to operation of the computer. The method may include simulating responsive to the input, that the machine has generated a message indicative of the condition. The method may include providing a further input which prevents performance of the carrying out step.

Abstract: A modeling method to improve the accuracy of timing analysis that more closely models timing information associated with layout parasitics that are connected to interface pins of a transistor-level subcircuit. A method is described for performing a hierarchical timing analysis of a circuit having a transistor-level subcircuit. Certain data (e.g., the layout parasitic data associated with interface nodes) associated with the transistor-level subcircuit are set aside. A timing model (timing arcs) of the transistor-level subcircuit is created without using these data. The timing analysis of the circuit is performed using a circuit analyzer. The circuit analyzer uses the timing model (timing arcs) and the layout parasitic data for the transistor-level subcircuit in the timing analysis. Thus, the layout parasitic data associated with the lower level subcircuit is preserved and used in the higher level circuit timing analysis to provide an accurate non-linear timing analysis of the layout parasitics.

Abstract: The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of simulating a digital circuit in such a way that the simulation is stopped at desired functions for subsequent analysis. A hardware design code describing the digital circuit is converted to an assignment decision diagram (ADD) representation that is then annotated with one or more control nodes that are used for maintaining control flow through a simulator. In this way, one or more break points are created that allow the simulator to stop at associated points in the simulation.

Abstract: A fast simulation method for single and coupled lossy transmission lines is based on triangle impulse responses. The method is used in simulating systems which can consist of large number of lossy transmission lines with frequency-dependent parameters which are placed in a high-speed IC package design.