Abstract: A low-voltage DC lighting system with identification addresses, comprising a smart controller, a terminal controller, a plurality of digital control switches connected with a low-voltage DC power supply through the terminal controller and controlled by the terminal controller and low-voltage DC lamps connected with each of the digital control switches respectively, each one of the smart controller and the terminal controller has a unique code, a storage space and an own CPU respectively, the terminal controller has a network interface connected to the smart controller, and the terminal controller exchanges information with the smart controller through the network interface, the smart controllers are also connected with each other via network interfaces, and the smart controller stores the identification addresses of every low-voltage DC lamps controlled by the terminal controller; the terminal controller comprises a network information receiving and transmitting module, a terminal calculating module and a lig

Abstract: A printed circuit board (1) with multiple electronic components (2, 2?, 2?, 2??, 2??) arranged on it in at least one group (G1, G2, G3), each of the electronic components (2, 2?, 2?, 2??, 2??) having a first and a second electrical component contact surface (3?, 3?) facing the printed circuit board (1), the component contact surfaces (3?, 3?) being connected with corresponding printed circuit board contact surfaces (6, 7, 8) arranged on the printed circuit board (1), successive electronic components (2, 2?, 2?, 2??, 2??) being connected in series to form a string, the string having a wave-shaped course, the electronic components (2, 2?, 2?, 2??, 2??) of the string being arranged on the printed circuit board (1) in the form of a matrix with at least two rows (Z1, Z2, Z3) and at least two columns (S1, . . . , S6), and the string alternately running up and down along columns (S1, . . . , S6) that are arranged next to one another.

Abstract: Lighting apparatuses each include an apparatus communicator and an apparatus controller. The apparatus communicator wirelessly transmits and receives information on operations of the lighting apparatuses. The apparatus controller interprets: a mesh profile which is a communications protocol for the lighting apparatus to transmit and receive the information to and from another lighting apparatus and a communication terminal forming a mesh network, and a user profile which is a communications protocol for the lighting apparatus and the communication terminal to communicate with each other, the user profile being set depending on the communication terminal.

Abstract: A control system including: a base including a central axis; a knob rotatably connected to the base, the knob rotatable about the central axis; a plurality of individually indexed light emitting elements distributed along the base perimeter and arranged to direct light radially outward of the central axis; a diffuser arranged radially outward of the light emitting elements; a wireless communication module enclosed between the knob and base; and a processor enclosed between the knob and base, the processor connected to the wireless communication mechanism and plurality of light emitting elements, the processor configured to individually control each light emitting element based on a control signal received from the wireless communication mechanism.

Abstract: A phononic transistor can be realized by arranging a row of cantilevered structures with attached magnets, elastically extending upward upon application of a magnetic repulsive force to the magnets. In the extended configuration, the phonons are transmitted from source to drain, while in the flattened configuration the phonons are blocked from transmission. A gate element controls the ON and OFF states of the phononic transistor.

Abstract: According to one embodiment, a level shift circuit includes a first transistor, a second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor and eighth transistor. The level shift circuit also includes a first capacitance element, a second capacitance element, third capacitance element and fourth capacitance element. The first through eighth transistors have a first conductivity type. The first through fourth transistors are included to a bi-stable multi-vibrator. The fifth through the eighth transistors are included to an active load for the differential input of the signal through the third capacitance element and the fourth capacitance element.

Abstract: Provided is a light emitting diode (LED) lighting fixture including a light engine, a plurality of LEDs, an LED driver, and a near field communication (NFC) electrically erasable programmable read only memory (EEPROM) circuit. The NFC EEPROM circuit provides an avenue for storing information pertaining to the LED light fixture that is easily accessible.

Abstract: The present disclosure provides a dimming controller and a backlight module having the same, capable of distributing lighting times of each LED channel to a period of time. The dimming controller can decrease the duration of the LED string of each LED channel while maintaining under the duty cycle, thereby reducing the damage to the transistors. Besides, the dimming controller can turn on the transistors of the LED channels at different time points to avoid the higher current fluctuations at the output end, thereby reducing the flicker of the LED strings.

Abstract: Technologies for field-programmable gate array (FPGA) processing include a computing device having a field-programmable gate array (FPGA) and a virtual FPGA controller (VFC). The computing device generates a user-specific platform profile (PP) that identifies one or more FPGA applications to be instantiated. The computing device synthesizes each FPGA application identified by the PP to generate a bit stream image that is associated with the PP and saves the bit stream image in a profile storage of the computing device. The computing device generates a virtual memory address that is indicative of the identified FPGA applications in response to saving the bit stream image. The VFC translates the virtual memory address to a user segment of the FPGA and a logical element (LE) offset within the user segment. The FPGA executes the bit stream associated with the PP with the FPGA at the LE offset. Other embodiments are described and claimed.

Abstract: A controller includes a connection determination unit configured to determine whether a device and a device control apparatus are directly communicatively connected to each other. The device control apparatus functions as a type 1 device control apparatus under a condition where the connection determination unit has determined that the device and the device control apparatus are directly communicatively connected to each other. On the other hand, the device control apparatus functions as a type 2 device control apparatus under a condition where the connection determination unit has determined that the device and the device control apparatus are not directly communicatively connected to each other.

Abstract: A voltage translator translates an input signal to an output signal spanning a wide range of low voltages. An input buffer receives the input signal. A level shifter provides an output control signal. A gate control circuit provides gate control signals. An output buffer provides the output signal. The level shifter includes a pair of cross coupled P-type metal oxide silicon (PMOS) transistors each in series with an N-type metal oxide silicon (NMOS) transistor. A third NMOS transistor is coupled between an upper rail and a drain of one PMOS transistor; the gate of the third NMOS transistor is controlled by a first input control signal. A fourth NMOS transistor is coupled between the upper rail and a drain of the other PMOS transistor; the gate of the fourth NMOS transistor is controlled by a second input control signal.

Abstract: In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal, the second positive supply voltage being floating with respect to the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.

Abstract: Systems and methods are provided for linking two components in a superconducting circuit. A plurality of circuit elements, each comprising one of an inductor, a capacitor, and a Josephson junction, are connected in series on a path connecting the two components. A plurality of tunable oscillators are connected from the path connecting the two components. Each tunable oscillator is responsive to a control signal to tune an associated resonance frequency of the tunable oscillator within a first frequency range, within which the two components are coupled, and within a second frequency range, within which the two components are isolated.

Abstract: Provided is a lighting apparatus. The lighting apparatus may provide an output voltage to lighting loads, and include: a converter configured to generate the output voltage using a driving signal; and a driving circuit configured to provide the driving signal, and spread the frequency of the driving signal by performing frequency dithering on the driving signal while changing the shape of an oscillation signal.

Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.

Abstract: An apparatus comprises multiple impedances and multiple pairs of transistors. Each pair connects to an impedance. Each pair includes high and low side transistors. The high side transistors and the low side transistors are connected each other and to a first terminal of the corresponding impedance, wherein second terminals of the impedances are connected to each other. The apparatus also comprises a staggered signal transistor driver to assert separate delayed high side signals to control inputs of the high side transistors. The delayed high side signals are time delayed with respect to each other. The driver asserts separate delayed low side signals to control inputs of the low side transistors.

Abstract: The present invention discloses a resistance calibration circuit.

Abstract: A method and a system are provided for monitoring a lighting system. Physical location information is received with respect to each lighting unit of the system. Supply voltage information is also received with respect to each lighting unit. Based on the physical location of each lighting unit and the supply voltage information, power network information is derived to identify cable routes between the lighting units and the locations of lighting cabinets along the cable routes.

Abstract: An inrush current control device for an IC chip having multiple functional units and M power switches comprises a programmable counter unit, a selector unit and an enable signal driving unit. The programmable counter unit counts a clock signal and sets a predetermined counting value. The selector unit is connected to the programmable counter unit and has N output ports for outputting N enable signals. The enable signal driving unit has N enable driving circuits correspondingly connected to the N output ports of the selector unit, and controlling on/off states of N groups of the M power switches. The programmable counter unit controls the selector unit to output the N enable signals to the N enable signal driving circuits at a predetermined time interval determined by the predetermined counting value to switch on the N power switches groups successively to reduce the transient inrush current.

Abstract: A technique relates to a router. The router includes a qubit signal distributor, a readout signal distributor, and diplexers communicatively coupled to the qubit signal distributor and the readout signal distributor.