Abstract: A bubble domain chip is designed to provide the components necessary to perform all essential data-base functions. Many cross-linked loops in parallel allow the interchange of distinct columns of information. The use of an on-chip decoder achieves effective interchangeability of distinct rows of information. Thus, the basic storage structure and access modes conform to the high-level view of data implied by the relational data model, resulting in simpler programming. In addition, a plurality of comparators are provided to the plurality of storage loops to perform context search simultaneously on all the loops. The simultaneous search and the restriction to output of only qualified data greatly reduces the query time.

Abstract: A data processing security system employs a secure enclosure, such as a vault, for all cryptographic processes, and the maintenance of digital information in storage outside of the enclosure in encrypted form and when not in use by the host computer system, where the information is used in plain text form and which communicates with the enclosed encryption system by a standard interface.

Abstract: A pulse generator for generating pulse groups with desired widths and relations (spacings) within and between the groups up to extremely high speeds and with a time accuracy of the order of nanoseconds e.g. in radar applications. It is purely digital and operates on a control frequency which may be derived from an internal crystal oscillator or may be externally supplied. The generator is divided into two main units, a first unit for determining the spacing of the pulse groups, and a second unit controlled by the first unit for determining the pulse widths and controlling pulse generator means. Different time space numbers and pulse widths numbers may be programmed into PROM memories of said units and may be selected by the same set of operating mode signals. The time spacing may also be optimized by means of an external computer controlling a further PROM holding information which may be combined with the time distance PROM information.

Abstract: A method of performing a fast interrupt in a digital data processor having the capability of handling more than one interrupt is provided. When a fast interrupt request is received a flag is set and the program counter and condition code registers are stored on a stack. At the end of the interrupt servicing routine the return from interrupt instructions retrieves the condition code register which contains the status of the digital data processor and checks to see whether the flag has been set or not. If the flag is set it indicates that a fast interrupt was serviced and therefore only the program counter is unstacked.

Abstract: A memory pack is provided having a random access memory connected between a positive power source terminal and a ground terminal, an addressing terminal coupled with the random access memory, and a data input/output terminal coupled with the random access memory. The memory pack further includes an LED energizing terminal, a light emission element which is connected between the LED energizing terminal and a positive power source terminal, the LED being lit by an energizing signal applied to the LED energizing terminal, a RAM energizing terminal and a photocoupler which is connected between the RAM energizing terminal and the random access memory and which responds to an energizing signal applied to the RAM energizing terminal to apply an output signal to the random access memory thereby to set the random access memory to be operative.

Abstract: A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a second delay line to delay the rectangular wave by a selectable predetermined delay period, a control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to that of the rectangular wave clock cycle period plus the period of the second predetermined delay. The addition of a synchronization circuit permits the clock cycle period to be dynamically selected during a clock cycle. This provides a rectangular train with the period of each clock cycle being any of the predetermined clock cycle periods independent of the clock cycle period of preceding or succeeding clock cycles.

Abstract: An improved multiprocessor bus arbiter which provides dynamically prioritized access for a plurality of processors to shared peripheral devices on a common bus through bus access switches. The arbiter includes logic circuitry to which incoming bus access request signals are coupled and a memory means which stores bus access status. The logic circuit determines bus access based on the input request signal and the stored information. The arbiter is adapted to provide a cycle shared mode of access or a lock out mode of access, as may be required.

Abstract: A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.

Abstract: A power failure detection and restart system for use with a microprocessor (microcomputer) control system includes first and second cascaded voltage comparators, the first of which responds to a drop in the supply voltage supplied to the microprocessor to produce an output pulse causing a software freeze of the microprocessor. The microprocessor operates in response to the software freeze pulse to transfer the contents of certain registers thereof to a battery protected memory for temporary storage therein. A positive feed-back circuit is used on the first voltage comparator to insure its rapid and complete change of state; and this change of state signal is applied through a time delay circuit to the second voltage comparator, which produces an output signal a predetermined time after the software freeze pulse is obtained from the first voltage comparator to reset the microprocessor to an initial circuit condition.

Abstract: A system and apparatus for compressing a binary data message generated by a digital input device is disclosed wherein a data message generated in a data terminal device as part of a merchandise transaction is examined on the basis of information content with all data relating to redundant information previously generated or known being deleted together with encoding of preselected portions of the non-redundant data results in the compression of the data to a minimum amount without losing the informational content of the original data thereby allowing the compressed data to be stored in a relatively small storage unit located in the data terminal device. A compressed data record is generated including an encoded start of record character which may signify, in addition to the start of the compressed data record, the type of merchandise transaction being processed.

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

Abstract: A memory system adapted to receive a radio frequency signal and produce a signal having a frequency related to the frequency of the received signal for an extended, predetermined period of time. The received signal is heterodyned to an intermediate frequency signal. The intermediate frequency signal is sampled and digitized by an analog-to-digital converter. One bit of each digitized sample has a logic state related to the polarity of the intermediate frequency signal. The bits associated with the samples are stored for a time interval beginning at a time the intermediate frequency signal changes polarity with a predetermined sense, i.e. the start of a complete cycle of the signal. A control signal is produced providing an indication of the portion of the bits stored in the shift register at the end of the time interval which is associated with complete cycles of the stored signal and the portion of the stored bits which is associated with an incomplete cycle of the stored signal.

Abstract: A plurality of sub-clock signals are derived from a main clock signal sou by advancing a shift register and a counter with pulses from the main clock source. The shift register is selectively loaded with a desired combination of sub-clock bits in response to a predetermined number of main clock pulses being supplied to the counter. The sub-clock signals are derived from output terminals at different stages of the shift register. The state of the sub-clock signals can be selectively frozen by decoupling pulses from the main clock source to inputs of the counter and shift register.

Abstract: A computer based process control system includes a digital event counter input circuit wherein a number of data sources are scanned. A sensed status of the individual input point is compared with the previous status of that point to determine if a change of status has occurred, indicative of an event to be counted. The previous status is stored in a dedicated register. If the comparison indicates that a countable event has occurred, a counter is incremented; also the dedicated register is updated to indicate the present status of the scanned point. The counter status is stored in an accompanying memory which may then be read out by an external device such as a processor.

Abstract: A device for use with a digital computer for storing standard software used by the computer and modifying the address portions of the standard software prior to transmission to the computer. The device includes a ROM package containing a ROM within which is stored a standard software subprogram written assuming it is stored at an absolute location in the computer's memory other than its actual location in the computer's memory system. Also included in the ROM package is a base register which can be loaded, under control of the operating system software, with an offset value reflecting the difference between the actual starting memory system location of the subprogram stored in the ROM and the assumed absolute starting location of the subprogram. Each ROM word includes an extra bit to indicate whether the corresponding data word contains an address requiring relocation. As a word is read out of ROM, a gating circuit tests whether an address relocation is required.

Abstract: A data processing unit in which the clock speed is selected to match the access times of the store units connected to it. This is achieved by means of a special terminal on each store unit, this terminal being internally grounded if the unit is of a slow access type, and open-circuited if the unit is of a fast access type.

Abstract: A disk address controller includes: a random access memory for storing the upper and lower limit addresses of the access area of each of processing units which are allotted to a disk unit, and storing the disk address specified by a disk input/output instruction from the processing unit; a read only memory for storing a microprogram corresponding to the disk input/output instruction; a microprocessor for executing the microprogram; disk channel units provided corresponding to the respective disk units; and a direct memory access control unit for performing data transfer with the disk unit via the disk channel. The disk address controller sets up the upper and lower addresses of the area arbitrarily allotted to the disk unit by the processing unit.

Abstract: Two asynchronously operating computers which are each controlled by timing periods produced by its own clock are each provided with a pulse treatment circuit which in response to a break signal, interrupts the computer operation during the following timing period. A buffer memory is used in order to transfer information from the first to the second of the computers. Because of the asynchronism there is a risk that the buffer memory becomes either totally occupied or unoccupied. The risk is eliminated by means of an address and break signal generator which generates addresses to control writing and reading of the buffer memory and generates break signals which are sent to the pulse treatment circuit of the first and second computer in order to inhibit information from being sent to the buffer memory when it is full or drawn from the buffer memory when it is empty.

Abstract: In a microprocessor based system, wherein at least one microprocessor is battery powered, a power strobe circuit includes an analog switch for connecting the battery to the microprocessor only during programmed task performance. Upon completion of task performance, the microprocessor generates signals which trigger the analog switch to open, thereby deenergizing the microprocessor and to enable an external timer. After a predetermined period of time, which may be fixed in the timer or programmed, the timer causes the switch to reclose, thereby energizing the microprocessor for performance of another programmed task.

Abstract: A microprocessor based program loader is connected to the memory data bus and memory address bus of a programmable controller. The program loader is responsive to commands entered through a keyboard to load and edit the programmable controller control program. A mode switch associated with the programmable controller provides a number of selectable positions which determine the mode of operation of the programmable controller and the functions that can be performed by the program loader. One of the positions on this mode switch enables the program loader through a control line to assume control of the mode selection. The operator can thus control the mode of operation through the program loader keyboard which may be located remotely from the programmable controller.