Abstract: An integrated circuit (IC) chip package comprises a plurality of IC chips mounted on a multilayer substrate. A plurality of covers are provided on the substrate and are positioned so as to cover at least one of the IC chips. External pins are provided on each of the covers, and each of the pins is connected to selected chips via first signal lines on the covers connecting the pins to the substrate, and second signal lines within the substrate connecting the first signal lines to the selected chips. The substrate may be provided with a heat exchanger or heat sinks at the underside thereof, the overall construction resulting in a cool operating IC chip package with numerous external terminals having short wiring lengths to the chips.

Abstract: A contact structure on indium-containing III-V semiconductor material is comprised of a four layer sequence consisting of an indium layer in direct contact with the semiconductor material, a zinc layer in contact with the indium layer, a chromium-nickel or chromium or palladium or platinum layer in contact with the zinc layer and a gold layer for external contacting with a lead. An exemplary embodiment of such contact structure exhibits specific contact resistance ranging between about 10.sup.-4 and 10.sup.-5 ohm.multidot. cm.sup.2.

Abstract: The invention is an improved light emitting device comprising a light emitting element mounted on a header wherein the improvement comprises a thin layer of copper overlying the surface of the header including both the base and the stud. A large increase in the yield of useable devices is obtained for a light emitting element mounted on the header which emits between about 1.0 and about 1.7 micrometers.

Abstract: A transistor package having input, reference (ground) and output terminals includes a ceramic base metallized to provide a ground plane and an isolated collector pad; and also includes a transistor die disposed on the pad. An equivalent output circuit of the transistor die describes an output impedance having a capacitive reactance. Pairs of wires are connected from the ground plane to the collector pad in series with DC blocking capacitors to provide an inductive reactance in parallel with the capacitive reactance of the transistor die. The pairs of wires are disposed in a transverse, preferably a substantially perpendicular, relationship and are connected to the collector pad at distributed, preferably uniformly distributed, positions along such area. This provides for a substantially uniform distribution of current throughout the transistor die and a substantially uniform junction temperature throughout the die.

Abstract: A porcelain coated steel substrate for receiving thick film printed circuit thereon includes thermally and electrically conductive pedestals which are in thermal and electrical contact with the steel core. The pedestal surface is coplanar with the porcelain coating so that a substantially continuous plane surface is present. This permits semiconductor chips readily to be mounted on the substrate, the pedestals serving as heat and electrical conductors to the substrate, and serves also to facilitate the deposition of thick film elements.

Abstract: Semiconductor component with a plurality of semiconductor elements disposed in a case having a metallic bottom being in heat-conducting contact with the semiconductor elements, electrical leads, and a leaf spring having ends and providing electrical pressure contact between the semiconductor elements and the leads, including yokes each holding a respective end of the spring, and at least two screws anchoring the yokes and the semiconductor elements to the bottom.