Patents Examined by E. J Kielin
  • Patent number: 6136688
    Abstract: The present invention is a method of capping with a high compressive stress oxide, a boron phospho-silicate glass (BPSG) interlayer dielectric (ILD) gapfill that has been deposited on a topographic silicon substrate, in order to eliminate the formation of cracks in subsequently deposited silicon nitride (SiN) layers, other subsequently deposited high tensile stress layers and cracks that result from other post-BPSG deposition high temperature processes.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: October 24, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Keng-Chu Lin, Kuang-Chao Chen, Rong-Wu Chien, Lian-Fa Hung, Pang-Yen Tsai, Ching-Chang Chang