Abstract: In an embodiment a method includes providing a semiconductor body, forming a sacrificial layer above a surface of the semiconductor body, applying a diaphragm on the sacrificial layer and removing the sacrificial layer by introducing an etchant into openings of the diaphragm, wherein applying the diaphragm comprises applying a first layer, reducing a roughness of a surface of the first layer facing away from the semiconductor body thereby providing a processed surface, and patterning and structuring the first layer to form the openings.

Abstract: A semiconductor structure comprises a substrate defining a first axis and a second axis in orthogonal relation to the first axis, first and second nanosheet stacks disposed on the substrate, a gate structure on each of the first and second nanosheet stacks, a source/drain region adjacent each of the first and second nanosheet stacks, a wrap-around contact disposed about each source/drain region and an isolator pillar disposed between the wrap-around contacts.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, and a carbonitride semiconductor layer. The first nitride semiconductor layer is over the substrate. The second nitride semiconductor layer is formed on the first nitride semiconductor layer and has a greater bandgap than that of the first nitride semiconductor layer. The carbonitride semiconductor layer is between the substrate and the first nitride semiconductor layer.

Abstract: An organic light-emitting diode (OLED) display device is provided, which includes an OLED display module, the OLED display module includes a plurality of sub-display sections, adjacent sub-display sections are dynamically connected to each other, and the sub-display sections can be expanded and integrated into a large-area display region, or dynamically accommodated to form at least one display section. By dynamically connecting multiple sub-display sections, a large-sized flexible display screen can be folded.

Abstract: An organic light-emitting diode (OLED) display panel, a manufacturing method thereof, and a display device are provided. The OLED display panel includes a substrate; an array functional layer; a light-emitting layer; a thin-film encapsulation layer; and a liquid crystal layer, which is disposed on the thin-film encapsulation layer, including a first liquid crystal region arranged on a non-pixel region and a second liquid crystal region arranged on a pixel region, wherein liquid crystal molecules positioned in the first liquid crystal region are aligned parallel to the substrate.

Abstract: A display panel includes a display region with a thin film transistor and a plurality of data lines and a non-display region. Thin film transistor includes a gate, a source region and a drain region, data lines include a plurality of first type data lines which are located at an edge of display region and close to a side of non-display region. First type data line includes a first sub-data line extending in a first direction, a conductive connection line extending in a second direction and a second sub-data line extending in a first direction. First sub-data line is connected with source region or drain region. A first insulating layer is between conductive connection line and first sub-data line. A second insulating layer is between second sub-data line and conductive connection line, and second sub-data line is closer to a central axis of display panel than first sub-data line.

Abstract: Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads.

Abstract: A display substrate, a method for manufacturing the display substrate, and a display device. The display substrate includes a first sub-pixel and a second sub-pixel, the first sub-pixel includes a first data line pattern, and the second sub-pixel includes a second data line pattern, a second electrode of the sixth transistor in the first sub-pixel is electrically connected to the anode pattern through the third conductive connection portion and the fourth conductive connection portion; in the first sub-pixel, an orthographic projection of the anode pattern on the substrate at least partially overlaps an orthographic projection of the second data line pattern on the substrate, and the orthographic projection of the anode pattern on the substrate at least partially overlaps an orthographic projection of a data line pattern adjacent to the second data line pattern along the first direction on the substrate.

Abstract: A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.

Abstract: A semiconductor device includes a substrate, a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other, an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other, a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer the lower channel insulating layer surrounding a lower slit, and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit. A width of the lower slit is greater than a width of the upper slit, and a thickness of the lower channel insulating layer is greater than a thickness of the upper channel insulating layer.

Abstract: A novel light-emitting device is provided. Alternatively, a light-emitting device with high emission efficiency is provided. Alternatively, a light-emitting device having a long lifetime is provided. Alternatively, a light-emitting device having low driving voltage is provided. A light-emitting device including an EL layer including a first layer, a second layer, a third layer, a light-emitting layer, and a fourth layer in this order from the anode side is provided. The first layer includes a first organic compound and a second organic compound. The fourth layer includes a seventh organic compound. The first organic compound exhibits an electron-accepting property with respect to the second organic compound. The HOMO level of the second organic compound is from ?5.7 eV to ?5.4 eV. The HOMO level of the seventh organic compound is ?6.0 eV or higher.

Abstract: A sensor module comprising: A sensor chip (5) is provided on an upper surface of the substrate (1). A lens (7) is provided above the sensor chip (5) such that a light receiving unit of the sensor chip (5) is positioned in a projection area. A lens cap (8) includes a cap body (8a) surrounding the sensor chip (5) to hold the lens (7), and a cap edge part (8b) protruding outward from a lower end part of the cap body (8a). An ultraviolet-curing type bonding agent (9) bonds the upper surface of the substrate (1) and a lower surface of the lens cap (8). A cutout (10) is provided on an outer side surface of the cap edge part (8b). The bonding agent (9) enters in the cutout (10).

Abstract: A method for fabricating a Pt nanorod electrode array sensor device includes forming planar metal electrodes on a flexible film, co-depositing Pt alloy on the planar metal electrodes via physical vapor deposition, and dealloying the Pt alloy to etch Pt nanorods from the deposited Pt alloy. A Pt nanorod electrode sensor device includes a plurality of porous Pt nanorods on a planar metal electrode forming a sensor electrode. The planar metal electrode is on a flexible substrate. An electrode lead on the flexible substrate extends away from the planar metal electrode. Insulation is around porous Pt nanorods an upon the electrode lead.

Abstract: A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.

Abstract: A method for fabricating a semiconductor device includes preparing a lower structure including an interconnection, forming a first contact plug coupled to the interconnection, and forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the lower structure. The method further includes forming an opening that penetrates the alternating stack and exposes the first contact plug, forming a sacrificial plug including a void in the opening, forming a contact hole that exposes the first contact plug by etching a portion of the sacrificial plug, and forming a second contact plug in the contact hole.

Abstract: There is provided a display device including a cover plate and a display panel; the cover plate includes a middle plane part, a first edge curved surface part, a second edge covered surface part and a corner curved surface part; the display panel includes a middle part, an edge part and a corner part; the middle part is arranged corresponding to the middle plane part; the edge part includes a first edge part and a second edge part; the first edge part and the first edge curved surface part are arranged correspondingly, and the second edge part and the second edge curved surface part are arranged correspondingly; the corner part and the corner curved surface part are correspondingly arranged; the middle part is in a display area; at least a portion of the edge part and the corner part adjacent to the middle part is in the display area.

Abstract: According to one embodiment, a display device includes a substrate, a pixel circuit, an insulating layer including a contact hole, a lower electrode connected to the pixel circuit via the contact hole, an upper electrode, an organic layer between the lower electrode and the upper electrode, a rib formed of an inorganic material and including an aperture, and a partition above the rib. The organic layer includes a first organic layer in contact with the lower electrode via the aperture and a second organic layer located on the partition and spaced apart from the first organic layer. The partition overlaps an entire of the contact hole in plan view.