Abstract: A contact hole is formed in a protective film 9 so as to communicate with an upper electrode 15. In the contact hole is formed a conductor 13 made of substantially the same material as used for the upper electrode 15, so as to communicate with the upper electrode 15 and extend to the outside of the contact hole. The conductor 13 is electrically connected to a memory cell transistor, by a wiring layer 14.

Abstract: An improved photo detector is provided by forming a tub of monocrystalline semiconductor material surrounded by a layer of monocrystalline material of opposite conductivity type. The improved structure is manufactured by means of a modified DIC process. The device may by made deep enough to absorb a large portion of the incident radiation near the PN junction without sacrificing a large number of photo-generated carriers to recombination.

Abstract: A circuit package comprises at least one IC chip bonded directly in a hole provided in a wafer such that the surface of the chip and the surface of the wafer are in the same plane thereby accommodating TAB bonding of the chip to bonding pads provided on the wafer. The structure can include multilayer circuitry on the wafer.

Abstract: In a microelectronic package of the type where Si-based integrated circuits are eutectically attached to a Pd/Au-based thick film conductor, a method of reducing the potential for thermal runaway is taught. The method involves increasing the surface area of the Pd to lower the Vbe rating. This reduces the potential for thermal runaway in subsequent integrated circuit operation. It has also been found that increasing the particle size of the Au component further decreases the Vbe rating.

Abstract: A metal-oxide-semiconductor field-effect device for constituting a single logic inverter stage. It includes a multidrain transistor operating in enhancement mode and a load transistor, both of monochannel metal-oxide-semiconductor structure. The inverter transistor comprises a single gate region and several drain regions. The single gate region and the single channel region of the inverter multidrain transistor are superimposed on both implantation planes separated by a thin insulating layer, entirely surround each drain region of the inverter multidrain transistor and are entirely surrounded by the single source region of the inverter multidrain transistor.

Abstract: The invention is concerned with methods for producing improved semiconductor devices. The invention is advantageously employable in the fabrication of insulated-gate field-effect transistor devices. The problem of accurately aligning the gate electrode over the channel region, lying between the source region and the drain region of a field effect transistor, is particularly addressed and solved. Accurate and precise field protection of all areas of the field-effect transistor surrounding the channel, source and drain regions is simply and effectively accomplished. The proper alignment of the gate electrode is largely accomplished by utilizing essentially the same mask structure to define the gate, source and drain regions. The same mask structure is utilized to define the area that is field protected.

Abstract: A transistor having input, reference and output terminals includes a ceramic base with a metallized area plated thereon and a transistor die supported on the metallized area. The metallized area and the transistor die provide in an equivalent output circuit of the transistor a shunt capacitance which in combination with other characteristics in the equivalent output circuit adversely affects the output impedance, internal losses, and bandwidth of the transistor. A reactance branch including an inductor is connected between the metallized area and the reference terminal to provide in the equivalent output circuit an inductance which resonates with the shunt capacitance. By thus reducing the influence of the shunt capacitance in the equivalent output circuit, the reactance branch increases the output impedance, decreases the internal losses, and increases the bandwidth of the transistor.

Abstract: A high inverse gain semiconductor device including a one conductivity semiconductor substrate having a major surface and a buried region formed in said substrate of relatively high concentration one conductivity impurities extending to said major surface. A one conductivity semiconductor layer is formed on said major surface, said layer having a planar surface. An opposite conductivity base region is formed in said layer overlying said buried region and extends to said planar surface. The base region has an outwardly notched handle-shaped portion extending outward from said base region into said body and extending to said planar surface. A one conductivity additional region formed entirely within said opposite conductivity base region extends within said base region to form a relatively uniform base region exclusive of said handle-shaped portion having a relatively narrow base width between said additional region and said layer.

Abstract: A large voltage swing across a typical planar transferred electron logic device is achieved by a nonlinear load resistor in series with the transferred electron device. The nonlinear load resistor includes a body of transferred electron effect material with an adjacent layer of high dielectric material. The layer is of sufficiently high dielectric material so that the load resistor so formed saturates at a current standoff point provided by the bias source of the logic device.

Abstract: A thyristor highly proof against dv/dt in which to prevent malignition due to the displacement current produced by the application of an abruptly rising forward voltage or the internal leakage current increasing with the temperature rise of the semiconductor substrate, an auxiliary electrode is provided to the intermediate region adjacent to one of the outermost regions of the semiconductor substrate to which two main electrodes, anode and cathode, are provided, the auxiliary electrode and the main electrode on the one outermost region being connected electrically, and a control region having the opposite conductivity type to that of the intermediate region is formed in the intermediate region between the auxiliary electrode and the main electrode on the one outermost region, the control region being provided with a gate electrode.

Abstract: A deep depletion insulated gate field effect transistor is made in a silicon layer on a sapphire substrate, so that its threshold voltage is relatively independent of the thickness of the silicon layer. The silicon layer has two parts, namely, a lower part adjacent to the sapphire substrate which is relatively lightly doped, and an upper part, preferably formed by ion implantation, having a doping concentration on the order of about 2 .times. 10.sup.15 atoms/cm.sup.3.

Abstract: A semiconductor memory cell, and a method for fabrication, including a one conductivity semiconductor body having a major surface and an opposite conductivity layer formed on said major surface said layer having a planar surface. Means extend from said planar surface through said layer to contact said body for isolating portions of said layer into first and second device regions. First and second device regions each include a one conductivity region formed in said device region extending to said planar surface, an opposite conductivity region formed within said one conductivity regions extending to said surface, and a metal-to-semiconductor contact carried by said device region at said planar surface. Lead means include means for ohmic interconnection of opposite conductivity regions formed in said first and second device regions, means for interconnecting said first device region and said one conductivity region formed in said second device region.

Abstract: An improved case member for a power semiconductor device is comprised of compacted powdered iron infiltrated with copper to provide good electrical and thermal contact for the semiconductor element and sufficient mechanical strength for use in a compression bonded encapsulation.

Abstract: A semiconductor diode matrix with only slight difference in the characteristics, and good reproducibility of the diodes, and small resistance of the matrix lines, in which the diodes are formed on strips of semiconductor material, located in the body of the dielectric base layer. Each strip is surrounded from the side of the base layer by a layer of material having higher conductivity than the semiconductor material of the strip.

Abstract: A monolithic two-phase charge coupled MNOS device having on a substrate an oxide layer having alternate relatively thin and thick regions thereof and a nitride layer thereon. Alternate electrodes for distributing, respectively, first and second phase clock signals are provided on the nitride layer. Each electrode overlays both a thin region and an adjacent thick region in the oxide layer. The MNOS devices formed by an electrode, the nitride layer, a thin oxide region in the oxide layer, and the substrate have electrically alterable threshold voltages, which permits electrical alteration of the surface potential pattern, so that the direction of transfer of a charge packet during the shifting operation may be electrically predetermined.

Abstract: Semiconductor devices containing integrated circuits are attached directly to external package leads by pressing simultaneously a plurality of groups of leads against bonding pads on a plurality of face-up semiconductor dice and heating the composite structures. Solder bumps on the bonding pads contain hard pedestals which prevent the overlying leads from being pushed into the faces of the semiconductor devices while the solder on the solder bumps melts to form the bonds between the leads and the underlying semiconductor dice. The process for carrying out this operation lowers significantly the cost of each packaged semiconductor device and the resulting structure is more reliable than structures of the prior art.

Abstract: An integrated circuit having a metal interconnect system formed with molybdenum engaging all contact areas of N conductivity type regions and aluminum engaging said molybdenum and engaging all contact areas of P conductivity type regions.

Abstract: The specification discloses an electrode configuration for a three phase charge coupled device having a channel for accommodating movement of charge packets. A first phase bus is formed on two levels and is disposed along one side of the channel and includes an array of first phase electrodes which span the channel on two levels. Second and third phase busses are disposed along the other side of the channel and include arrays of second and third phase electrodes formed on two levels which span the channel and which extend between adjacent ones of the first phase electrodes.

Abstract: A field effect transistor with spaced source and drain regions of a first type conductivity in a monocrystalline semiconductor body having a background impurity of a second opposite type conductivity, the improvement being a buried layer of a second type conductivity impurity having an average concentration higher than the impurity concentration of the background impurity that is located just beneath the insulating layer in the field regions of the device and at a greater depth in the gate region, the depth in the gate region being approximately equal to the thickness of the field insulating layer less the thickness of the gate insulating layer.

Abstract: A semiconductor package device characterized by improved operation at ultra-high frequencies and by improved heat dissipation, includes an auxiliary metal stud mounted on a metal substrate. A semiconductor element, such as a field-effect transistor or bipolar transistor, is mounted on the auxiliary stud and has at least one electrode thereof electrically connected to the stud.