Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

Abstract: A method for manufacturing asolar cell includes texturing a front surface of a semiconductor substrate having a first conductive type dopant by using a dry etching method, forming an emitter layer by ion-implanting a second conductive type dopant into the front surface of the semiconductor substrate, forming a back passivation film on a back surface of the semiconductor substrate; and forming a first electrode electrically connected to the emitter layer and a second electrode being in partial contact with the back surface of the semiconductor substrate.

Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.

Abstract: According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.

Abstract: Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure.

Abstract: A FinFET including a substrate, a plurality of isolators, a gate stack, and strained material portions is provided. The substrate includes at least two fins thereon. The isolators are disposed on the substrate, and each of the insulators between the fins has a recess profile. The gate stack is disposed over portions of the fins and over the insulators. The strained material portions cover the fins revealed by the gate stack. In addition, a method for fabricating the FinFET is provided.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: A deep ultraviolet LED with a design wavelength of ? is provided that includes a reflecting electrode layer, a metal layer, a p-type GaN contact layer, and a p-type AlGaN layer that are sequentially stacked from a side opposite to a substrate, the p-type AlGaN layer being transparent to light with the wavelength of ?; and a photonic crystal periodic structure that penetrates at least the p-type GaN contact layer and the p-type AlGaN layer. The photonic crystal periodic structure has a photonic band gap.

Abstract: A semiconductor device formed on a silicon carbide substrate that has a front surface on which an electrode is provided and a back surface on which an electrode is provided includes a drain layer, a drift layer, a base layer, a gate electrode that is located in a trench that extends from the front surface into the drift layer and is insulated by an insulating film, a source layer, a buried layer that is provided between the drift layer and the base layer and is formed such that the depth from the front surface to an end thereof on the side of the drift layer is greater than the depth from the front surface to a distal end of the trench, and a first epitaxial layer that is provided between the buried layer and the base layer and has a higher impurity concentration than the buried layer.

Abstract: An improved organic light-emitting display apparatus prevents damage of wiring due to a mask during the manufacturing process, and a manufacturing method thereof. An organic light-emitting display apparatus includes a display unit formed on a substrate, a pad unit formed at one outer side of the display unit on the substrate, a wiring unit formed as a multilayer structure on the substrate to couple the display unit to the pad unit, a thin film encapsulating layer covering the display unit, and a protrusion unit that does not overlap the uppermost layer of wiring of the multilayered wiring unit.

Abstract: In an optical substrate (1), a concave-convex structure (12) including a plurality of independent convex portions (131 to 134) and concave portions (14) provided between the convex portions (131 to 134) is provided in a surface. The average interval Pave between the adjacent convex portions (131 to 134) in the concave-convex structure (12) satisfies 50 nm?Pave?1500 nm, and the convex portion (133) having a convex portion height hn satisfying 0.6 h?hn?0 h for the average convex portion height Have is present with a probability Z satisfying 1/10000?Z?1/5. When the optical substrate (1) is used in a semiconductor light-emitting element, dislocations in a semiconductor layer are dispersed to reduce the dislocation density, and thus internal quantum efficiency IQE is improved, and a waveguide mode is removed by light scattering and thus the light the extraction efficiency LEE is increased, with the result that the efficiency of light emission of the semiconductor light-emitting element is enhanced.

Abstract: A semiconductor device includes a substrate having a first dopant type, a first gate electrode and second gate electrode formed over the substrate and spatially separated from each other, a first region of a second dopant type, having a pocket of the first dopant type, formed in the substrate between the first and second gate electrodes, the pocket being spaced apart from the first and second gate electrodes, a silicide block over the first region, a source region formed in the substrate on an opposing side of the first gate electrode from the first region and having the second dopant type, a drain region formed in the substrate on an opposing side of the second gate electrode from the first region, the drain region having the second dopant type, and a second pocket of the first dopant type formed in the drain region adjacent to the second gate electrode.

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Abstract: Provided is a semiconductor device that can suppress a leakage current more than has been achieved before. A semiconductor device 22 includes a first carrier holding layer 48, which is arranged on a lower electrode 47, is in contact with a lower electrode 47 via a first interface 49, and includes majority carriers of one type, and a second carrier holding layer 57, which is arranged on the first carrier holding layer 48, defines a second interface 58 constituting a conduction path to the first carrier holding layer 48, and includes majority carriers of the other type. The first interface 49 has its outline within the outline of the first carrier holding layer 48 when seen in a plan view in a direction that is orthogonal to a surface of the substrate, and the second interface 58 has its outline within the outline of the first carrier holding layer 48 when seen in the plan view.

Abstract: A semiconductor device is formed, the semiconductor device including: an SOI substrate; field insulating films that are formed on the SOI substrate and that separate a plurality of element formation regions; first and second HV pMOSs, and first and second LV pMOSs that are formed in the plurality of element formation regions; a first interlayer insulating film and a second interlayer insulating film formed on the SOI substrate; a mold resin formed on the second interlayer insulating film; and conductive films that are formed on the first interlayer insulating film and that are interposed between the plurality of element formation regions, and the field insulating films and mold resin.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and an insulating wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The insulating wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.

Abstract: An organic light emitting display device may include: a cell array comprising gate lines and data lines intersecting each other on a substrate so as to define a plurality of pixel areas, a plurality of thin film transistors formed at intersections between the gate lines and the data lines to correspond to the plurality of pixel areas, and a protective film evenly formed over the substrate to cover the thin film transistors; a plurality of first electrodes formed such that portions of an metal oxide layer corresponding to emission areas of the respective pixel areas, is made conductive, the metal oxide layer evenly disposed on the protective film; a bank constituting the remaining portion of the metal oxide layer in which the first electrodes are not formed and formed so as to have insulating properties; an emission layer formed over the metal oxide layer; and a second electrode formed on the emission layer so as to face the first electrodes.

Abstract: A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.

Abstract: In pixels that are two-dimensionally arranged in a matrix fashion in the pixel array unit of a solid-state imaging element, a photoelectric conversion film having a light shielding film buried therein is formed and stacked on the light incident side of the photodiode. The present technique can be applied to a CMOS image sensor compatible with the global shutter system, for example.

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate including a flash memory region and a capacitor region. A flash memory cell is arranged over the flash memory region and includes a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell. The flash memory cell also includes a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer. A capacitor is arranged over the capacitor region and includes: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and separated from one another by a capacitor dielectric layer. The capacitor dielectric layer and control gate dielectric layer are made of the same material.