Abstract: A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.
Type:
Grant
Filed:
December 28, 1998
Date of Patent:
October 2, 2001
Assignees:
Infineon Technologies North America Corp., International Business Machines Corporation