Patents Examined by Edgardo Orizt
  • Patent number: 6057583
    Abstract: A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The source and drain regions of the transistor are configured upon a semiconductor substrate, and the transistor channel is within the substrate. A protective dielectric layer is deposited over the semiconductor substrate. Source/drain trenches are formed in the protective dielectric layer and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which are preferably formed from a low-resistance metal.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: May 2, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Jr.