Abstract: A method and a global server for deduplicating multiple storage servers are disclosed. The global server maintains information regarding a set of hash values, each hash value being associated with a data chunk of data stored in the global server and/or the storage servers, receive, from one or more of the storage servers, a request to modify the information with respect to one or more hash values, accumulate and sort metadata related to the one or more requests, modifies the information with respect to the one or more hash values, based on the accumulated metadata when the accumulated metadata reaches a determined size.

Abstract: Examples described herein relate to memory thin provisioning in a memory pool of one or more dual in-line memory modules or memory devices. At any instance, any central processing unit (CPU) can request and receive a full virtual allocation of memory in an amount that exceeds the physical memory attached to the CPU (near memory). A remote pool of additional memory can be dynamically utilized to fill the gap between allocated memory and near memory. This remote pool is shared between multiple CPUs, with dynamic assignment and address re-mapping provided for the remote pool. To improve performance, the near memory can be operated as a cache of the pool memory. Inclusive or exclusive content storage configurations can be applied. An inclusive cache configuration can include an entry in a near memory cache also being stored in a memory pool whereas an exclusive cache configuration can provide an entry in either a near memory cache or in a memory pool but not both.

Abstract: Methods and systems are provided for configuring static memory in a device by analyzing a set of functionalities of a first device based on at least one use case wherein the at least one use case are associated with configuring available static memory in processing at least one functionality of the first device; configuring at least a first profile composed of the first part for memory allocation of the available static memory to a first processor, and a second part for memory allocation of the available static memory to a second processor of the first device; selecting the first profile either automatically or via a graphical user interface (GUI) by identifying a set of performance characteristics related to the functionality, and implementing the memory allocation by the first profile in processing the at least one functionality in the use case by the first device.

Abstract: Replicating a dataset in a storage system operating in a reduced power mode, including: detecting that the storage system should enter the reduced power mode; entering the reduced power mode; and performing, while in the reduced power mode, one or more data replication operations associated with the dataset, including selecting, from amongst a plurality of data communication mechanisms, a data communication mechanism to utilize for performing the one or more data replication operations.

Abstract: As front-end write IO operations occur, the front-end write IO operations are allocated slots of global memory and mapped to slices of back-end tracks. A back-end write destage manager allocates back-end slices to aging buckets based on the number of write operations pending destage for the given back-end slice. As global memory destage pressure increases, the back-end write destage manager uses a weighted bucket table to increase the weight back-end slices with larger numbers of front-end tracks that are occupying the larger slots of global memory. This results in back-end slices that are owed data from front-end tracks occupying larger front-end slot sizes to be placed in aging buckets with shorter aging times. These back-end slices are thus more quickly selected to be destaged, thus causing a larger percentage global memory slots of the largest slot size to be made available to be allocated to subsequent host IO write operations.

Abstract: The present disclosure relates to a method, a device and a computation apparatus for allocating a space address to data in a memory, where the computation apparatus is included in a combined processing apparatus, which includes a general interconnection interface and other processing apparatuses. The computation apparatus interacts with other processing apparatuses to jointly complete computations specified by the user. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and the other processing apparatuses, and is used for storing data of the computation apparatus and other processing apparatuses. The technical solutions of the present disclosure improve utilization of storage space of the memory.

Abstract: The present disclosure relates to a storage device that optimally maintains a size of debugging data. Disclosed is a memory controller, including a first interface may communicate with a first external device; a second interface may generate a signal for controlling an operation of a second external device; a first volatile memory buffer; and a processor may generate and store the telemetry log data in the first volatile memory buffer; move and store the telemetry log data stored in the first volatile memory buffer to a first non-volatile memory buffer, when a size of the telemetry log data stored in the first volatile memory buffer is greater than or equal to a threshold size; and set the threshold size based on at least one among a number of telemetry logs stored in the first volatile memory buffer and a rising momentum of the number of the telemetry logs.

Abstract: Data protection operations based on direct storage access. Data protection operations that involve large data transfers are optimized or improved by transferring the data using a communication path that includes direct access to disks of a storage array. This avoids latencies associated with transferring data through the layers of the storage array. The locations of the data to be transferred are identified and provided to an appliance. The appliance can then read and transfer the data over a communication path that includes direct disk access.

Abstract: A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.

Abstract: A data storage method includes that a first device generates N check units for M data units, where M and N are both positive integers, and M+N=K. The first device stores the K units in K hard disk modules in the storage system, where the K units include the M data units and the N check units. Each of the K hard disk modules stores one of the K units. Each hard disk module includes an interface module and a hard disk, and the interface module communicates with the hard disk.

Abstract: Techniques are disclosed relating to smashing atomic operations. In some embodiments, cache control circuitry caches data values in cache storage circuitry and receive multiple requests to atomically update a cached data value according to one or more arithmetic operations. The control circuitry may perform updates to a cached data value based on the multiple requests, in response to determining that the one or more arithmetic operations meet one or more criteria and store operation information that indicates a most-recent requested atomic arithmetic operation for the updated data value. The control circuitry may, in response to an event, flush, to a higher level in a memory hierarchy that includes the cache storage circuitry both: the updated data value and the operation information. This may advantageously smash atomic operations at the cache and reduce operations to the higher-level cache or memory (which may be the actual coherence point for atomic requests).

Abstract: Techniques for dynamically configuring a multi-site storage system such as a metro cluster using input/output (IO) response time (RT) hints from a host computer. The techniques include receiving IO RT hints at each storage appliance of the multi-site storage system from the host computer, which is initially identified as “local” or “remote” relative to a physical location of the storage appliance. The techniques further include modifying, by the storage appliance, an initial local or remote identification of the host computer relative to the physical location of the storage appliance based on the received IO RT hints, dynamically changing, by the storage appliance, states of IO paths between the host computer and nodes of the storage appliance based on the modified local or remote identification of the host computer, and providing, by the storage appliance, notification of the changed states of the IO paths to the host computer.

Abstract: A memory device may include a plurality of non-volatile memory devices and a controller. The controller may be configured to generate first parity data for a portion of a data block stored in a plurality of memory blocks of the plurality of non-volatile memory devices, store the first parity data in a swap block that includes one or more non-volatile memory devices of the plurality of non-volatile memory devices, generate second parity data for the data block, store the second parity data in the swap block, perform a partial read back of the data block, store, after performing the partial read back, the second parity data in a subset of the plurality of memory blocks, and release the first parity data from the swap block after storing the second parity data in the subset of the plurality of memory blocks.

Abstract: A second memory stores a plurality of input data sets DSi composed of a plurality of pieces of input data. N multiply-accumulate units are capable of performing parallel processings, and each performs a multiply-accumulate operation on any one of the plurality of weight parameter sets and any one of the plurality of input data sets. A second DMA controller transfers the input data set from the second memory to the n multiply-accumulate units. A measurement circuit measures a degree of matching/mismatching of logic levels among the plurality of pieces of input data contained in the input data set within the memory MEM2, the sequence controller controls the number of parallel processings by the n multiply-accumulate units based on a measurement result by the measurement circuit.

Abstract: A method of applying an address space to data storage in a non-volatile solid-state storage is provided. The method includes receiving a plurality of portions of user data for storage in the non-volatile solid-state storage and assigning to each successive one of the plurality of portions of user data one of a plurality of sequential, nonrepeating addresses of an address space. The address range of the address space exceeds a maximum number of addresses expected to be applied during a lifespan of the non-volatile solid-state storage. The method includes writing each of the plurality of portions of user data to the non-volatile solid-state storage such that each of the plurality of portions of user data is identified and locatable for reading via the one of the plurality of sequential, nonrepeating addresses of the address space.

Abstract: The present disclosure provides a system. The system includes a memory device and a controller. The memory device is configured to store memory data and includes a plurality of memory modules. Each of the memory modules includes a first memory block and a second memory block. The controller includes a processor and a memory. The controller is operatively coupled to the plurality of memory modules. In an operation on redundant array of independent disks (RAID), the controller is configured to generate a first check code based on memory data in the first memory block of the plurality memory modules, generate a second check code based on memory data in the second memory block of the plurality memory modules, and generate an additional check code based on the first check code and the second check code.

Abstract: In at least one embodiment, processing can include: determining that an inactive decref (decrement reference count) MDL (metadata log) of decref MD (metadata) updates stored in memory is unable to be destaged to a decref tier of non-volatile storage in a first destage phase of a two phase destage process; and responsive to determining that the inactive decref MDL is unable to be destaged to the decref tier, performing bypass destage processing of the inactive decref MDL, wherein said bypass destage processing includes directly applying MD updates of the inactive decref MDL to corresponding MD pages stored persistently in a MD page store and wherein said bypass destage processing omits storing the inactive decref MDL on the decref tier.

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allows an application of a computer system to create a series of one or more logs of writes to one or more memory locations of a memory device. The logs may comprise the values at the end of the log interval of the one or more memory locations that were written to during a log interval. In some examples, the logs do not include intermediate writes to the one or more memory locations (only the final value) and do not include values of memory locations that were not written to during the interval. After an event, software can apply these logs to a copy of the original memory region state to recover the contents of the locations at any of the logged points. These logs may be useful to recreate the state of the memory at various points during the application's execution.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.

Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, where the storage medium is organized as one or more partitions, including at least one secure partition. The partitions are defined by a corresponding set of pre-specified physical memory blocks of the storage medium. The data storage device also includes a data path configured to provide data communication between a host computer system and the storage medium of the data storage device. A partition controller of the data storage device is coupled to a switch. In response to an actuation of the switch, the partition controller is configured to cause the data storage device to selectively transition between: a secure mode in which the set of physical memory blocks of each secure partition is connected to the host via the data path; and a non-secure mode in which the set of physical memory blocks of each secure partition is disconnected from the host via the data path.