Abstract: In this network, each cell (k.sub.n) receives a current (I.sub.ph (k)) from a photodetector (12) and provides an output current (S.sub.n) representative of the local constrast in the zone in which this cell is situated. According to the invention, each cell comprises adjustable conductances determining an output current (I.sub.out (k)) depending in a monotonic increasing saturating manner of the ratio between photodetector current (I.sub.ph (k)) and a mean current (I.sub.mean (k)), said ratio representing the local contrast at the cell under consideration. The first of the conductances (P2) is regulated by the current (I.sub.ph (k)) flowing in the photodetector. Calculating means in each cell generate a mean current (I.sub.mean (k)) from the currents flowing in the photodetectors of the relevant cell and in at least some of the neighboring cells. This current is representative of the mean illumination to which the network is subjected. The conductances (P.sub.4a, P.sub.

Abstract: A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself.

Abstract: An automated method for checking cytological system autofocus integrity. The automated method includes the steps of checking focus illumination integrity, checking focus camera Modulation Transfer Function, checking focus camera position integrity, and checking closed loop accuracy. Checking focus illumination integrity includes checking focus illumination system integrity, and checking a focus noise floor level. Checking focus camera position integrity includes checking focus camera longitudinal separation, and checking focus camera lateral separation. Checking focus camera position integrity includes checking focus filter frequency response.

Abstract: A photosemiconductor relay of the present invention comprises a light-emitting unit for emitting light therefrom, a light-receiving control circuit for providing a predetermined potential difference or more between a first connecting terminal and a second connecting terminal during a light-receiving period and electrically connecting the first and second connecting terminals to each other in response to the non-reception of the light, and a switching circuit for electrically connecting a first output terminal and a second output terminal to each other in response to the reception of the predetermined potential difference or more and restricting a load current flowing between the first and second output terminals to a predetermined value or less. Thus, since a current of a predetermined value or more does not flow into a load circuit connected between the output terminals, the load circuit is prevented from malfunctioning and the switching circuit is promptly turned off.

Abstract: A fully differential, low voltage ECL gate (300) receives differential input signals (A, Ax, B, Bx) and provides them to first and second differential amplifiers (306, 328). The first differential amplifier (306) amplifies and level shifts the differential input (A, Ax) to provide a differential output (OUTx). The second differential amplifier amplifies the second differential input (B, Bx) to provide an amplified output, OUT. The amplified output signal, OUT, provides a different voltage level than that provided by amplified level shifted output signal, OUTx. The amplified level shifted output (OUTx) of the first differential amplifier (306) is then compared to the amplified output (OUT) of the second differential amplifier (328) to provide either an AND gate or an OR gate function.

Abstract: An optical pick-up apparatus includes a light source, an objective lens, a beam splitter, a detector, a first optical compensating device and a second optical compensating device. The objective lens converges a light beam emitted from the light source at one point on an optical axis. The beam splitter separates the light beam emitted from the light source from a returning light reflected on an optical disc. The detector detects the returning light separated from the light beam emitted from the light source. The first optical compensating device has a convex aspherical surface represented by X.alpha.R.sup.4 and is located on an optical path where the light beam is emitted from the light source. The second optical compensating device has a concave aspherical surface represented by +.alpha.R.sup.4 and is located on an optical path where the light beam is emitted from the light source.

Abstract: A semiconductor integrated circuit device has a differential logic circuit formed by multi-stage series-gating logic circuits each composed of bipolar transistors whose emitters are connected in common and level shift circuits each for shifting a level of an input signal that is inputted from the outside in correspondence to one of the stage logic circuits of the differential logic circuit, and for supplying the level-shifted input signal to the base of one of the bipolar transistors of the corresponding logic circuit. In particular, a potential difference between the level-shifted signals inputted to the bases of the bipolar transistors of each of the stage logic circuits is determined, as a level shift rate, to be lower than a built-in potential between the base and emitter of each of the bipolar transistors thereof. The semiconductor integrated circuit device is operative on a lower supply voltage, without significantly degrading the functions and performance thereof.

Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

Abstract: A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source.

Abstract: A programmable logic array comprises a PLA area having a plurality of banks wherein each of the bank has an array of a discharge typed logic circuit for decoding a micro-code, a command code is inputted to each bank every cycle for executing a predetermined command, and each bank outputs bank selection data for determining by which bank a command of a next cycle be decoded at the previous cycle, and a control circuit for selecting one bank for decoding the command code of the next cycle from the plurality of banks based on the bank selection data of each bank in the previous cycle, and for sending a command code to only the selected one bank to perform discharge of a discharge typed logic circuit, thereby stopping operations of other banks.

Abstract: A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control.

Abstract: A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.

Abstract: An input/output circuit communicates an external input signal to an internal signal and converts an internal signal to an external output signal. In one embodiment, the input/output circuit has a power supply terminal, and an input terminal that is coupled to an output terminal via a conductor. A pull-up circuit is coupled to the power supply terminal and the conductor, and includes a PMOS transistor having an N-well, where the pull-up circuit is configured to selectively pull-up the output signal. A pull-down circuit is coupled to a ground terminal and the conductor, and is configured to selectively pull-down the output signal.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

Abstract: A solid state relay includes a diode for emitting light, a photothyristor circuit responsive to the light from the diode for turning on and outputting a first output signal, the photothyristor circuit having two photothyristors connected to each other in parallel in an opposing direction and a triac circuit responsive to the photothyristor circuit for turning on and outputting a second output signal.

Abstract: The demodulator comprises two parallel channels which have in each channel:two transverse parallel filters whose weighting coefficients are cos (.omega.p.tau.) and sin (.omega.p.tau.) with for one channel .omega.=.omega..sub.Z =2.pi.F.sub.Z, and for the other channel .omega.=.omega..sub.A =2.pi.F.sub.A ; anda device ensuring the squaring of the signal from each filter.

Abstract: A crystal oscillator is provided a portion of which is fabricated in monolithic integrated circuit form. The circuit is temperature-compensated and utilizes a single 5 volt DC power supply compatible with NMOS and TTL voltage levels. The duty cycle of the oscillator may be varied between approximately 30 and 70 percent.