Abstract: An integrated circuit fabrication process is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, sidewall spacers are formed laterally adjacent opposed sidewall surfaces of the gate electrode. An interlevel dielectric is then formed above the semiconductor substrate and selectively removed from above active regions of the semiconductor substrate to form an opening. Source and drain implant areas are formed self-aligned with the opposed sidewall spacers. A metal silicide layer may be formed across upper surfaces of the gate conductor and source and drain areas, a second interlevel dielectric deposited in the opening, and contacts formed through the second interlevel dielectric to the metal silicide.

Abstract: A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.