Patents Examined by Edwards J Dudek, Jr.
  • Patent number: 11977766
    Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: May 7, 2024
    Assignee: NVIDIA Corporation
    Inventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
  • Patent number: 11977762
    Abstract: A Logical Unit Number (LUN) division method and device includes checking and adjusting a connection manner and numbers of Serial Attached Small Computer System Interface (SCSI) (SAS) connections of storage enclosures and a controller, so as to make a maximum output bandwidth of each storage enclosure consistent (Si); querying controller port identifiers and storage enclosure identifiers (S2); creating a Mdisk array, and adding the corresponding controller port identifier and the corresponding storage enclosure identifier for each Mdisk (S3); logically dividing a storage space in the Mdisk array to create a volume, and dividing the volume into LUNs, whereby Mdisks that form the LUNs are made to come from different storage enclosures and different controller ports (S4); and mapping the LUNs to a host (S5).
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: May 7, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Yi Feng
  • Patent number: 11972294
    Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Angelo Della Monica, Paolo Papa, Carminantonio Manganelli, Massimo Iaculo
  • Patent number: 11972122
    Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yu-Chung Lien, Ching-Huang Lu, Zhenming Zhou
  • Patent number: 11972123
    Abstract: Methods, systems, and devices for row address latching for multiple activate command protocol are described. A memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. The memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. The memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kwang-Ho Cho, Miki Matsumoto
  • Patent number: 11966597
    Abstract: A data service implements a configurable data compressor/decompressor using a recipe generated for a particular data set type and using compression operators of a common registry (e.g., pantry) that are referenced by the recipe, wherein the recipe indicates at which nodes of a compression graph respective ones of the compression operators of the registry are to be implemented. The configurable data compressor/decompressor provides a customizable framework for compressing data sets of different types (e.g., belonging to different data domains) using a common compressor/decompressor implemented using a common set of compression operators.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: April 23, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Dmitri Pavlichin, Shubham Chandak, Itschak Weissman, Christopher George Burgess
  • Patent number: 11960393
    Abstract: A flash device includes user storage space for storing user data and over provisioning space for garbage collection within the flash device. The flash device receives an operation instruction, and then performs an operation on user data stored in the user storage space based on the operation instruction. Further, the flash device identifies a changed size of user data after performing the operation. Based on the changed size of data, a target adjustment parameter is identified. Further, the flash device adjusts the capacity of the over provisioning space according to the target adjustment parameter.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: April 16, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jianhua Zhou, Po Zhang
  • Patent number: 11960724
    Abstract: A device for detecting zone parallelity includes a detection control circuit configured to generate respective first and second requests for first and second zones among a plurality of zones included in a solid state drive (SSD). An SSD controller is configured to control the SSD by generating a first command and a second command corresponding to the first request and the second request, respectively, and to schedule the first command and the second command. The detection control circuit determines zone parallelity of the first and second zones using response characteristics of the responses of the SSD to the first request and the second request. The response characteristics may include a latency of a response.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: April 16, 2024
    Assignees: SK hynix Inc., Industry-Academic Cooperation Foundation, Dankook University
    Inventors: Jongmoo Choi, Myunghoon Oh
  • Patent number: 11960412
    Abstract: A method for managing data in a NAND flash storage system is provided. The method includes one or more of receiving an empty data segment directive at a storage controller, returning a data string including data of a predetermined logic level in response to a read command requesting to read data associated with a logical identifier included in the empty data segment directive, maintaining an index of mapping between the logical identifier and a physical storage location, updating the index to indicate data at the physical storage location does not need to be preserved, monitoring one or more physical storage locations, including the physical storage location, to determine a percentage of the one or more physical storage locations that do not need to be preserved, and initiating garbage collection on the one or more physical storage locations in response to the percentage reaching a threshold. The empty data segment directive includes a logical identifier associated with the physical storage location.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: April 16, 2024
    Inventors: David Flynn, Jonathan Thatcher, Michael Zappe
  • Patent number: 11954348
    Abstract: Techniques are provided for combining data block and checksum block I/O into a single I/O operation. Many storage systems utilize checksums to verify the integrity of data blocks stored within storage devices managed by a storage stack. However, when a storage system reads a data block from a storage device, a corresponding checksum must also be read to verify integrity of the data in the data block. This results in increased latency because two read operations are being processed through the storage stack and are being executed upon the storage device. To reduce this latency and improve I/O operations per second, a single combined I/O operation corresponding to a contiguous range of blocks including the data block and the checksum block is processed through the storage stack instead of two separate I/O operations. Additionally, I/O operation may be combined into a single request that is executed upon the storage device.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: April 9, 2024
    Assignee: NetApp, Inc.
    Inventors: James Alastair Taylor, Suhas Girish Urkude
  • Patent number: 11947830
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, group a plurality of KV pair data based on a data clustering value, aggregate the grouped plurality of KV pair data, and program the aggregated plurality of KV pair data to the memory device. A length of the KV pair data is less than a size of a flash management unit (FMU). The KV pair data includes a key and a value. Each KV pair data of the plurality of KV pair data has a length less than the size of the FMU. The received KV pair data is stored in a temporary location and grouped together in the temporary location. The grouping is based on a similarity of characteristics of plurality of KV pair data.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: David Avraham, Alexander Bazarsky, Ran Zamir
  • Patent number: 11947812
    Abstract: A system including: one or more processors; a memory storing instructions that, when executed by the one or more processors are configured to cause the system to: receive a plurality of user names and a plurality of anonymized user identifiers; receive a plurality of user attributes associated with one or more users of the plurality of users; receive a first plurality of hash values that uniquely identify an association between each user attribute and one or more users; receive a first request for a listing of user names associated with a first user attribute; receive a first secret key; generate a second plurality of hash values; determine a first subset of the first plurality of hash values that match the second plurality of hash values; generate a first graphical user interface including the listing of user names; and transmit the first graphical user interface to the first user device.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: April 2, 2024
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventors: Carla S. Erb, Sheel Shah, James E. Deaver, II, Caleb J. Cockrill, Aaron Woodard, Samantha Bennett, Christopher Halima, Andrew Moore, Daniel Hazeley
  • Patent number: 11941258
    Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including detecting a failure of a key-value store, identifying a non-filled zone of the memory device resulting from the failure, wherein the non-filled zone stores, in the key-value store, at least one of: an uncommitted key block or an uncommitted value block, and recovering the non-filled zone to obtain a recovered zone.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Pierre Labat, Nabeel Meeramohideen Mohamed, Steven Moyer
  • Patent number: 11941264
    Abstract: A data storage apparatus with a variable computer file system is disclosed. The variable computer file system adopts the concept of a dedicated sub-file system and is activated or deactivated according to whether authentication is granted. Each dedicated sub-file system is activated or deactivated according to whether authentication is granted, and is recognized by a host computer. Deactivated dedicated sub-file systems cannot be recognized or accessed by the host computer. Accordingly, since a third party accessing the host computer cannot access a dedicated sub-file system without possessing a means for activating the dedicated sub-file system, security is greatly strengthened.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: March 26, 2024
    Inventor: Deok Woo Kim
  • Patent number: 11941270
    Abstract: A data storage device includes a non-volatile memory device having a number of memory dies. The data storage device further includes a controller. The controller is configured to poll each of the memory dies at a first predetermined rate for a thermal status bit and determine whether the thermal status bit of at least one memory die of the number of memory dies is an active thermal status bit activated. The controller is further configured to reduce the operating performance of the at least one memory die in response to determining that the thermal status bit of the at least one memory die of the plurality of memory dies is the active thermal status bit.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: March 26, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Niles Yang
  • Patent number: 11934321
    Abstract: A memory management method is provided, which includes assigning separate virtual addresses to processes in user space, include to a file system configured to read/write to persistent storage. Virtual memory objects (VMOs) are created in user space that are backed by a user space pager service. Such objects including pages representing a file associated with information maintained in persistent storage. A pager manages reading/writing to persistent storage. The pager populates pages for a given VMO using data retrieved from persistent storage. Upon populating the pages, a state of the VMO is set to a clean state. Upon writing to the pages, the state of the VMO is set to a dirty state. Upon initiating writing back to persistent storage, the state of the VMO is set to an awaiting clean state. Upon ending the writing back, the state of the VMO is set to clean.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: March 19, 2024
    Assignee: GOOGLE LLC
    Inventors: Rasha Eqbal, Adrian Danis, Christopher James Suter
  • Patent number: 11934680
    Abstract: Embodiments of the systems and methods disclosed herein includes a NAND flash memory having a boot volume. The boot volume can include a primary boot partition, a secondary boot partition, and a rootdisk partition. The primary boot partition can be configured to receive a kernel component of a file. The secondary boot partition can be configured to receive a copy of the kernel component of the file. The rootdisk partition can be configured to receive a root filesystem of the file.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: March 19, 2024
    Assignee: ARRIS Enterprises LLC
    Inventors: Walter H. Anderes, Richard P. Rementilla, David L. Berger
  • Patent number: 11934679
    Abstract: A method, computer program product, and computing system for dividing a volume into a plurality of segments. The plurality of segments may be assigned to a plurality of nodes of a multi-node storage system. One or more input/output (IO) request paths for accessing the plurality of segments may be defined based upon, at least in part, assigning the plurality of segments to the plurality of nodes.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: March 19, 2024
    Assignee: EMC IP Holding Company, LLC
    Inventors: David Meiri, Vinay G. Rao, Sanjib Mallick
  • Patent number: 11928337
    Abstract: A method for managing a data record in a computer system comprises: at least one computing server for hosting a computer session running with an operating system having a deduplication index and managing access to a session storage space; a shared storage space; an administration server for administering the shared storage space, executing a data management program; the computer session executing an interception program implementing the following steps: intercepting a read call to read at least one data record transmitted in the session; accessing the deduplication index and determining whether the data record is recorded in the shared storage space; if so, reading, from the deduplication index, the address of the data record in the shared storage space and redirecting the read call to this address; if not, overlooking the read call so that it is processed by the operating system.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 12, 2024
    Assignee: SHADOW
    Inventor: Arnaud Lamy
  • Patent number: 11928340
    Abstract: Apparatus and methods for managing data in a computer system are disclosed. An example apparatus is to at least: facilitate storage of first subsidiary data, the first subsidiary data representing information related to a customer account; facilitate storage of second subsidiary data, the second subsidiary data representing at least a portion of the information related to the customer account; determine a geographic location of a computing device that is remote to the data storage device; determine whether the geographic location of the computing device satisfies a predefined criterion; and, when the geographic location of the computing device satisfies the predefined criterion, change the first subsidiary data and change the second subsidiary data.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: March 12, 2024
    Assignee: PointsBet Pty Ltd.
    Inventor: Manjit Gombra Singh