Patents Examined by Elias M Ullach
  • Patent number: 9142560
    Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Michael Launsbach, Daniel M. Nelson