Abstract: A method of fabricating a bottom electrode of a capacitor, in which a semiconductor substrate is provided wherein a transistor is formed thereon and the transistor contains a source/drain region. A dielectric layer having a contact hole is formed over the substrate wherein a portion of the source/drain region is exposed by the contact hole. A doped polysilicon layer is formed over the substrate. An insulating layer is formed on the doped polysilicon layer. An amorphous silicon layer is formed on the insulating layer. The amorphous silicon layer, the insulating layer and the doped polysilicon layer are defined to form a main structure of the bottom electrode. Amorphous silicon spacers are formed on sidewalls of the main structure. A hemispherical grained silicon layer is formed on the amorphous silicon layer and the amorphous silicon spacers.

Abstract: A method for fabricating a semiconductor device having asymmetric source-drain extension regions includes the formation of a conformal layer of spacer forming material over a gate electrode. Nitrogen atoms are directionally introduced into the sidewall spacer material to form nitrogenated regions within the sidewall spacer material. The gate electrode casts a shadow over a portion of the sidewall spacer material adjacent to an edge of the gate electrode that is opposite from the direction of introduction of the nitrogen atoms. The shadow region of the sidewall spacer material remains free of nitrogen atoms. The shadow region of the sidewall spacer material is converted into a sidewall spacer by isotropically etching away the nitrogenated regions, while not substantially etching the shadow region. The asymmetrically formed sidewall spacer can then be used to mask a portion of the substrate adjacent to the drain edge of the gate electrode.

Abstract: The depth of a denuded layer with respect to a relatively defective bulk region of a monocrystalline semiconductor wafer is estimated in a nondestructive way. The depth is determined by measuring the lifetime or diffusion length of injected excess minority charge carriers on a surface of the wafer having such a denuded layer and on a different portion of the surface of the wafer from where the denuded layer has been previously stripped-off by lapping and/or etching. The depth is calculated through a best-fit procedure or through numerical processing of the measurement results on the basis of the diffusion equations of excess minority carriers.

Abstract: In a semiconductor device manufacturing method includes the steps of uniformly applying a first photoresist onto a first layer on a semiconductor substrate, a first resist pattern is formed out of the first photoresist by using a first photomask. The first layer is etched by using the resist pattern, thereby forming a first pattern. A second photoresist is uniformly applied onto the semiconductor substrate where the first pattern is formed. A second resist pattern is formed out of the second photoresist by using a second photomask. The first pattern is etched by using the second photoresist, thereby forming a second pattern constituted by the first layer. A semiconductor device fabricated by this method is also disclosed.

Abstract: In a method of manufacturing a semiconductor device in which a capacitor having a storage electrode is formed on a semiconductor substrate, silicon films are formed on the semiconductor substrate and at the same time first and second endpoint marker layers for dividing the silicon films into three parts in the direction of thickness are formed by using a material different from the material of the silicon films. The silicon films including the first and second endpoint marker layers are etched. The etching depth of the silicon films is controlled based on the type of etched material, thereby forming the storage electrode.

Abstract: A method of fabricating a DRAM capacitor. A conductive layer and an amorphous silicon layer are formed on a substrate having a dielectric layer. The amorphous silicon layer and the conductive layer are etched to form a region of a capacitor to expose a portion of the dielectric layer. An opening with a profile having a wider upper portion and a narrower lower portion is formed within the conductive layer, and through the opening, the dielectric layer is then etched through to form a node contact window to expose the substrate. An amorphous silicon spacer is formed on the sidewall of conductive layer of the region of the capacitor and fills the node contact window. A selective HSG-Si, a dielectric layer and a polysilicon layer are formed to achieve the fabrication of the capacitor. The conductive layer, the amorphous silicon layer and the HSG-Si serve as a lower electrode of the capacitor and the polysilicon layer serves as an upper electrode of the capacitor.

Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.

Abstract: A method of manufacturing a cylindrical shaped capacitor includes the steps of providing a substrate that already has a polysilicon plug and a word line formed thereon, and then forming an insulation layer and a first dielectric layer over the substrate. Thereafter, the first dielectric layer is patterned to form an opening. Then, a first conductive layer and a second dielectric layer are deposited in sequence over the first dielectric layer and the opening. Next, the first conductive layer and the second dielectric layer are etched back to form spacers on the sidewalls of the opening. Subsequently, etching is carried out down through the opening using the sidewall spacers as a mask until the polysilicon plug is exposed. After that, a second conductive layer is formed over entire substrate, and then the second conductive layer is etched back so that only a portion of the second conductive layer and the first conductive layer remain.

Abstract: The invention relates to a microelectronic integrated sensor, in which a cantilever is formed. To avoid mechanical stress during the production process, the cantilever is disposed freely movably in the sensor. To that end, a support for retaining the cantilever and lateral and upper motion limiters are provided, which prevent the cantilever from slipping off the support. The invention also relates to a method for producing such a sensor.

Abstract: A method of fabricating a self-aligned capacitor of a DRAM cell is provided. First, a landing pad and a bit line are formed on a semiconductor substrate. An insulating layer is formed on the landing pad and the bit line. A photoresist layer is formed on the insulating layer and the pattern of the photoresist layer is transferred to the insulating layer. A via hole is formed in the insulating layer using the photoresist layer as a mask to expose the landing pad. Spacers are formed on the sidewalls of the via hole by deposition and self-align etching back. A conductive layer is formed in the via hole. The conductive layer on the insulating layer is removed to form a bottom electrode of a capacitor.

Abstract: A method for planarizing the surface of a semiconductor wafer is disclosed. It involves the steps of: (a) applying a coating solution containing a polymeric material on a semiconductor wafer having a non-planar surface; (b) curing the polymeric material to cause the polymeric material to become a hardened polymeric material; (c) subjecting the hardened polymeric material to a N.sub.2 O gas plasma treatment, so that an outer portion of the hardened polymeric material can be polished by a conventional CMP slurry which is typically intended for polishing silicon oxide; and (d) polishing the N.sub.2 O gas plasma treated polymeric material using a conventional CMP slurry. This method allows conventional CMP slurries to be used for the chemical-mechanical polishing of the chemically more inert polymeric material, thus eliminating stocking and potential compatibility problem. It also advantageously allows the unaffected portion of the polymeric material to serve as a self-provided etch stop.

Abstract: A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

Abstract: A method to fabricate double poly gate high-density multi-state flat mask ROM cells on a silcon substrate is disclosed. The method comprises the following steps. Firstly, an in-situ n+ first polysilicon/pad oxide layer is deposited on the silicon substrate, and then an ARC layer such as nitride layer is deposited to improve the resolution during the lithography process for pateterning a first formed word line. After forming a plurality of dual nitride spacers on sidewalls of the first patterned gate, a first photoresist coating on all resultant surfaces except the two predetermined regins, a first boron or BF.sub.2.sup.+ coding implant into the silicon substrate is carried out. The photoresist is then stripped and an oxidaiton process conducted in O.sub.2 ambient to grow oxide layers on all surfaces of the silicon substrate using the nitride layer as a hard mask.

Abstract: A method and apparatus for preventing charge damage to a protected structure during processing of a semiconductor device. A first source/drain region of a protection transistor is coupled to a protected transistor gate. A second source/drain region of the protection transistor is coupled to ground. The protection transistor is then turned on during the processing of the device to ground the protected transistor gate.

Abstract: The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form source/drain and bitline diffusion structures for use in pillar memory cells. Additionally, in another embodiment, the present invention is used to form source/drain and plate diffusion structures in pillar memory cells. Both preferred embodiments deposit conformal photoresist on a pillar structure and use an off-axis exposure process to recess a dopant source layer to the proper depth along the pillar. The recessed dopant source layer can then be used to form the source/drain/bitlines diffusions or source/drain/plate diffusions in the pillar memory device.

Abstract: A self-aligned SOI device with body contact and silicide gate. The SOI device is formed using an ordinary substrate such as silicon. A silicide gate is self-aligned and formed from re-crystallization of nickel and amorphous silicon. The self-aligned silicide gate includes gate contact areas, and is self-aligned with respect to the gate opening, the source and drain regions and a nitride isolation layer. Nickel spacers deposited adjacent the isolation layer, and amorphous silicon deposited between the nickel spacers, form the self-aligned silicide gate through a silicidation process.

Abstract: A method of fabricating deep trench capacitors of high density Dynamic Random Access Memory (DRAM) cells is disclosed: first, deep trenches are formed on a silicon substrate by using oxide and nitride as etching masks, then, an ONO capacitor dielectric layer is deposited inside the trench, a first polysilicon layer as storage node is then deposited to fill the bottom of the trench, thereafter, dielectric collars are formed on the sidewalls of the trench, next, a sacrificial stud is formed inside the trench, the dielectric collars are then recessed to expose the contact area for the trench capacitor and access transistor, next, the sacrificial stud is removed by wet etching, followed by a second polysilicon deposition overlaying the first polysilicon, finally, the second polysilicon layer is etchback to a height slightly lower than the substrate surface to complete the trench capacitor formation.

Abstract: A method is provided for forming a polysilicon gate. A stacked gate with a first polysilicon layer/an oxide layer/a second polysilicon layer multiple structure is formed. The invention provides another method for forming a polysilicon gate, in which a first polysilicon layer is formed and waits for a period of time. Then, a second polysilicon layer is formed on the first polysilicon layer. A grain boundary is formed between the first polysilicon layer and the second polysilicon layer. The invention provides still another method for forming a polysilicon gate, in which a polysilicon layer is formed at the temperature of about 600-700.degree. C. and the pressure of about 1-5 torr to form a small-grained polysilicon layer. The three methods for forming a polysilicon gate can prevent the heavy ions from passing through the polysilicon gate and the gate oxide layer into the substrate while performing a pre-amorphization implant process.

Abstract: A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.

Abstract: A process is described for the manufacture of a capacitor having low V.sub.cc. Said process is fully compatible with standard IC manufacturing and introduces minimum modification thereto. The process involves the formation of a capacitor having both upper and lower electrodes that comprise layers of a metal silicide. The lower electrode is formed as a byproduct of the SALICIDE process while the upper electrode is formed by first laying down a layer of polysilicon followed by a layer of a silicide-forming metal such as titanium, cobalt, or tungsten. Sufficient of the metal must be provided to ensure that all of the polysilicon gets transformed to silicide.